An information processing apparatus includes a processor. The processor configured to allocate, to a process, a first number of first divided regions from among a plurality of divided regions obtained by division of a cache, and determine, based on an address of each data block corresponding to the process and the first number, a storage destination of the data block corresponding to the process from among the first divided regions. The processor configured to determine a second number that is a divisor of the first number, identify, for the individual first divided regions after the reduction, second divided regions from among the first divided regions before the reduction, determine data blocks to be stored in the individual first divided regions after the reduction by allocating data blocks to the first divided regions after the reduction from the corresponding second divided regions in ascending order of purging order.

A method of controlling a cache is disclosed. The method comprises receiving a request to allocate a portion of memory to store data. The method also comprises directly mapping a portion of memory to an assigned contiguous portion of the cache memory when the request to allocate a portion of memory to store the data includes a cache residency request that the data continuously resides in cache memory. The method also comprises mapping the portion of memory to the cache memory using associative mapping when the request to allocate a portion of memory to store the data does not include a cache residency request that data continuously resides in the cache memory.

The invention provides a processor including a prediction table, a prediction logic circuit, and a prediction verification circuit. The prediction table has a plurality of sets respectively corresponding to a plurality of cache sets of a cache memory in the cache system, each of the sets has a plurality of confidence values, and the prediction table provides the confidence values of a selected set according to the index. The prediction logic circuit receives the confidence values of the selected set, and generates a prediction result by judging whether each of the confidence values of the selected set is larger than a threshold value or not. The prediction verification circuit receives the prediction result, generates a correct/incorrect information according to the prediction result, and generates an update information according to the correct/incorrect information. Wherein, the prediction verification circuit updates the confidence values of the prediction table according to the update information.

The present disclosure provides a memory data access apparatus and method thereof. The memory data access apparatus includes a cache memory and a processing unit. The processing unit is configured to: execute a memory read instruction, wherein the memory read instruction includes a memory address; determine that access of the memory address in the cache memory is missed; determine that the memory address is within a memory address range, wherein the memory address range corresponds to a data access amount; and read data blocks corresponding to the data access amount from the memory address of a memory.

A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.

A memory controlling device of a computing device including a CPU, a memory, and a flash-based storage device is provided. The memory controlling device includes an address manager and an interface. The address manager aggregates a memory space of the memory and a storage space of the storage device into an expanded memory space, and handles a memory request for the expanded memory space from the CPU by using the memory space of the memory as a cache for the storage space of the storage device. The interface is used to access the memory and the storage device.

Systems, apparatuses and methods provide for technology that determines that first data associated with a first security domain is to be stored in a first permutated cache set, where the first permuted cache set is identified based on a permutation function that permutes at least one of a plurality of first cache indexes. The technology further determines that second data associated with a second security domain is to be stored in a second permutated cache set, where the second permuted cache set is identified based on the permutation function. The second permutated cache set may intersect the first permutated cache set at one data cache line to cause an eviction of first data associated with the first security domain from the one data cache line and bypass eviction of data associated with the first security domain from at least one other data cache line of the first permuted cache set.

Storage circuitry comprises an array of storage locations arranged in rows and columns, a row buffer comprising a plurality of entries each to store information from a storage location at a corresponding column of an active row of the array, and comparison circuitry responsive to a tag-matching command specifying a tag value to compare the tag value with information stored in each of a subset of two or more entries of the row buffer. The comparison circuitry identifies which of the subset of entries, if any, is a matching entry storing information matching the tag value. This allows memory technologies such as DRAM to be used more efficiently as a set-associative cache.

A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.

A processor includes a prediction table, a prediction logic circuit, and a prediction verification circuit. The prediction table has a plurality of sets, each of the sets has a hot way number, at least one warm way number, and at least one confidence value corresponding to the at least one warm way number. The prediction logic circuit generates a prediction result by predicting if the at least one warm way number is an opened way. The prediction verification circuit generates a correct/incorrect information according to the prediction result, and generates an update information according to the correct/incorrect information. The prediction verification circuit updates the hot way number, the at least one warm way number and the at least one confidence value of the at least one warm way number according to the update information.