According to one general aspect, an apparatus may include a front end logic section comprising a main-branch target buffer (BTB). The apparatus may also include a micro-BTB separate from the main BTB, and configured to produce prediction information associated with a branching instruction and mark prediction information as verified when one or more conditions are satisfied. Wherein the front end logic section is configured to be, at least partially, powered down when the data stored by the micro-BTB that results in the prediction information is marked as previously verified.

A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls a refresh operation so that a data refresh does not occur for the clean data only banks or the refresh rate is reduced for the clean data only banks. Partitions that store dirty data can also store clean data; however, other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.

A MMU may read page descriptors (using virtual addresses as an index) in a burst mode from page tables in a system memory. The page descriptors may include intermediate physical addresses (IPAs, in stage 1) and corresponding physical addresses (PAs, in stage 2). The virtual address in conjunction with page table base address register is used to index page descriptors into main memory. The MMU may identify a first group of contiguous IPAs beginning at a base IPA and a second group of contiguous IPAs beginning at an offset from the base IPA. The first and second groups may be separated by at least one IPA not contiguous with either the first or second group. The MMU may read a first PA from the page tables that corresponds to the base IPA. The MMU may store an entry in a buffer that includes the PA and a first linearity tag.

A memory controlling device of a computing device including a CPU, a memory, and a flash-based storage device is provided. The memory controlling device includes an address manager and an interface. The address manager aggregates a memory space of the memory and a storage space of the storage device into an expanded memory space, and handles a memory request for the expanded memory space from the CPU by using the memory space of the memory as a cache for the storage space of the storage device. The interface is used to access the memory and the storage device.

A microprocessor includes a branch target buffer (BTB). Each BTB entry holds a tag based on at least a portion of a virtual address of a block of instructions previously fetched from a physically-indexed physically-tagged set associative instruction cache using a physical address that is a translation of the virtual address, a translated address bit portion of a set index of an instruction cache entry from which the instruction block was previously fetched, and a way number of the instruction cache entry from which the instruction block was previously fetched. In response to a BTB hit based on a fetch virtual address, the BTB provides a translated address bit portion of a predicted set index that is the translated address bit portion of the set index from the hit on BTB entry and a predicted way number that is the way number from the hit on BTB entry.

According to one general aspect, an apparatus may include a first cache configured to store data. The apparatus may include a second cache configured to, in response to a fill request, supply the first cache with data, and an incoming fill signal. The apparatus may also include an execution circuit configured to, via a load request, retrieve data from the first cache. The first cache may be configured to: derive, from the incoming fill signal, address and timing information associated with the fill request, and based, at least partially, upon the address and timing information, schedule the load request to attempt to avoid a load-fill conflict.

A microprocessor includes a cache memory and a control module. The control module makes the cache size zero and subsequently make it between zero and a full size of the cache, counts a number of evictions from the cache after making the size between zero and full and increase the size when the number of evictions reaches a predetermined number of evictions. Alternatively, a microprocessor includes: multiple cores, each having a first cache memory; a second cache memory shared by the cores; and a control module. The control module puts all the cores to sleep and makes the second cache size zero and receives a command to wakeup one of the cores. The control module counts a number of evictions from the first cache of the awakened core after receiving the command and makes the second cache size non-zero when the number of evictions reaches a predetermined number of evictions.

A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The cache access includes the processor(s) generating, based on historical data related to the address, a prediction for a location of the data in the cache that is a set identifier of a predicted cache set. The processor(s) concurrently perform a data access to the cache to retrieve sets in the cache. The processor(s) confirm(s) that the retrieved include the predicted cache set. The processor(s) utilize(s) the set identifier to select data from the predicted set.

A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The cache access includes the processor(s) generating, based on historical data related to the address, a prediction for a location of the data in the cache that is a set identifier of a predicted cache set. The processor(s) concurrently perform a data access to the cache to retrieve sets in the cache. The processor(s) confirm(s) that the retrieved include the predicted cache set. The processor(s) utilize(s) the set identifier to select data from the predicted set.

Techniques are disclosed relating to set-associative caches in processors. In one embodiment, an integrated circuit is disclosed that includes a set-associative cache configured to receive a request for a data block stored in one of a plurality of ways within the cache, the request specifying an address, a portion of which is a tag value. In such an embodiment, the integrated circuit includes a way prediction circuit configured to predict, based on the tag value, a way in which the requested data block is stored. The integrated circuit further includes a tag array circuit configured to perform a comparison of a portion of the tag value with a set of previously stored tag portions corresponding to the plurality of ways. The tag array circuit is further configured to determine whether the request hits in the cache based on the predicted way and an output of the comparison.