Cache memory clock generation circuits for reducing power consumption and read errors in cache memory are provided. In one aspect, a cache memory clock generation circuit employs detector circuit configured to receive a way address and generate a one way hit signal indicating if cache read request results in a single way hit. Clock and enable circuit is configured to generate a cache clock signal in response to a system clock signal and a cache enable signal, and generate a cache read enable signal in response to the cache clock signal and a read enable signal. Gating circuit is configured to generate a read clock signal in response to one way hit signal, cache clock signal, and cache read enable signal. Sense amplifier clock generation circuit is configured to generate sense amplifier clock signal in response to the read clock signal having a defined pulse width.

The lookup of accesses (including snoops) to cache tag ways is serialized to perform one (or less than all) tag way access per clock (or even slower). Thus, for a N-way set associative cache, instead of performing lookup/comparison on the N tag ways in parallel, the lookups are performed one tag way a time. Way prediction is utilized to select an order to look in the N ways. This can include selecting which tag way will be looked in first. This helps to reduce the average number of cycles and lookups required.

The invention provides a processor including a prediction table, a prediction logic circuit, and a prediction verification circuit. The prediction table has a plurality of sets respectively corresponding to a plurality of cache sets of a cache memory in the cache system, each of the sets has a plurality of confidence values, and the prediction table provides the confidence values of a selected set according to the index. The prediction logic circuit receives the confidence values of the selected set, and generates a prediction result by judging whether each of the confidence values of the selected set is larger than a threshold value or not. The prediction verification circuit receives the prediction result, generates a correct/incorrect information according to the prediction result, and generates an update information according to the correct/incorrect information. Wherein, the prediction verification circuit updates the confidence values of the prediction table according to the update information.

A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.

A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)-way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.

A processing device includes a cache implementing a set of at least three cache slices. Each cache slice is to store a corresponding set of cache lines. The cache further includes cache control logic coupled to the set of at least three cache slices. The cache control logic is to map addresses of an address space to the cache such that each address within the address space maps to a corresponding strict subset of two or more cache slices of the set of cache slices.

Cache memory clock generation circuits for reducing power consumption and read errors in cache memory are provided. In one aspect, a cache memory clock generation circuit employs detector circuit configured to receive a way address and generate a one way hit signal indicating if cache read request results in a single way hit. Clock and enable circuit is configured to generate a cache clock signal in response to a system clock signal and a cache enable signal, and generate a cache read enable signal in response to the cache clock signal and a read enable signal. Gating circuit is configured to generate a read clock signal in response to one way hit signal, cache clock signal, and cache read enable signal. Sense amplifier clock generation circuit is configured to generate sense amplifier clock signal in response to the read clock signal having a defined pulse width.

Systems and methods for accessing a cache include determining if a current access of the cache will satisfy an expected relationship with a next access of the cache, wherein the cache is a set-associative cache comprising multiple ways. The next way for the next access is stored in a next way field associated with the current access. If the expected relationship will be satisfied, such as a sequential relationship which will be satisfied in the case of an instruction cache when the current access does not cause a change in control flow, the next way for the next access is retrieved from the next way field associated with the current access. The next way of the cache is then directly accessed using the retrieved next way.

A set associative cache memory, comprising: an array of storage elements arranged as M sets by N ways, each set belongs in one of L mutually exclusive groups; an allocation unit allocates the storage elements in response to memory accesses that miss in the cache; each memory access has an associated memory access type (MAT) of a plurality of predetermined MAT; a mapping, for each group of the L mutually exclusive groups: for each MAT, associates the MAT with a subset of the N ways; and for each memory access, the allocation unit allocates into a way of the subset of ways that the mapping associates with the MAT of the memory access and with one of the L mutually exclusive groups in which the selected set belongs.

Optimizing cache energy consumption in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a way lookup table (WLUT) circuit that is configured to receive an effective address (EA) for a memory access request. The WLUT circuit determines that a tag portion of the EA corresponds to a tag of a WLUT entry among a plurality of WLUT entries. In response, the WLUT circuit transmits a predicted way indicator of the WLUT entry to a cache controller. The cache controller accesses, in a set among a plurality of sets of a cache memory device corresponding to a set portion of the EA, only a predicted tag way among a plurality of tag ways of the cache memory device indicated by the predicted way indicator and only a predicted data way among a plurality of data ways of the cache memory device indicated by the predicted way indicator.