An integrated circuit includes a first array of resistors, a second array of resistors, and a plurality of interface circuits electrically coupled between the first array of resistors and the second array of resistors. Each interface circuit among the plurality of interface circuits is configured to receive a signal from the first array of resistors, and apply an analog voltage corresponding to the signal to the second array of resistors.

A device, comprising: an array of cells, wherein the cells are arranged in columns and rows; wherein each cell comprises a memristive device; an interfacing circuit that is coupled to each cell of the array of cells; wherein the interfacing circuit is arranged to: receive or generate first variables and second variables; generate memristive device input signals that once provided to memristive devices of the array will cause a change in a state variable of each of the memristive devices of the cells of the array, wherein the change in the state variable of each of the memristive devices of the cells of array reflects a product of one of the first variables and one of the second variables; provide the memristive device input signals to memristive devices of the array; and receive output signals that are a function of at least products of the first variables and the second variables.

A device, comprising: an array of cells, wherein the cells are arranged in columns and rows; wherein each cell comprises a memristive device; an interfacing circuit that is coupled to each cell of the array of cells; wherein the interfacing circuit is arranged to: receive or generate first variables and second variables; generate memristive device input signals that once provided to memristive devices of the array will cause a change in a state variable of each of the memristive devices of the cells of the array, wherein the change in the state variable of each of the memristive devices of the cells of array reflects a product of one of the first variables and one of the second variables; provide the memristive device input signals to memristive devices of the array; and receive output signals that are a function of at least products of the first variables and the second variables.

An electronic circuit includes a circuit to receive an analog input signal responsive to an analog oscillating signal and to generate an analog output signal, AD converters to perform AD-conversion with respect to the analog oscillating signal, the analog input signal, and the analog output signal to generate a digital oscillating signal, a digital input signal, and a digital output signal, at least one first adjustor to adjust a phase of the digital oscillating signal through the Hilbert transform, a second adjustor to adjust a phase of the digital input signal through the Hilbert transform, a third adjustor to adjust a phase of the digital output signal through the Hilbert transform, a first mixer circuit to multiply the output of the first adjustor and the output of the second adjustor, and a second mixer circuit to multiply the output of the first adjustor and the output of the third adjustor.

An electronic circuit includes a circuit to receive an analog input signal responsive to an analog oscillating signal and to generate an analog output signal, AD converters to perform AD-conversion with respect to the analog oscillating signal, the analog input signal, and the analog output signal to generate a digital oscillating signal, a digital input signal, and a digital output signal, at least one first adjustor to adjust a phase of the digital oscillating signal through the Hilbert transform, a second adjustor to adjust a phase of the digital input signal through the Hilbert transform, a third adjustor to adjust a phase of the digital output signal through the Hilbert transform, a first mixer circuit to multiply the output of the first adjustor and the output of the second adjustor, and a second mixer circuit to multiply the output of the first adjustor and the output of the third adjustor.

There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.

There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.

Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.

There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.

An apparatus comprising a first electrical oscillator, a second electrical oscillator, at least one ferroelectric capacitor coupled between the first electrical oscillator and the second electrical oscillator, a ferroelectric capacitor of the at least one ferroelectric capacitor comprising a first terminal, a second terminal, and a ferroelectric material between the first terminal and the second terminal; and a detector coupled to the first electrical oscillator and second electrical oscillator, the detector to produce an output based on a state of the first electrical oscillator and the second electrical oscillator.