This application relates to the field of artificial intelligence technologies, and discloses a machine learning model search method, a related apparatus, and a device. In the method, before model search and quantization, a plurality of single bit models are generated based on a to-be-quantized model, and evaluation parameters of layer structures in the plurality of single bit models are obtained. Further, after a candidate model selected from a candidate set is trained and tested, to obtain a target model, a quantization weight of each layer structure in the target model may be determined based on a network structure of the target model and evaluation parameters of all layer structures in the target model, a layer structure with a maximum quantization weight in the target model is quantized, and a model obtained through quantization is added to the candidate set.

This application relates to the field of artificial intelligence technologies, and discloses a machine learning model search method, a related apparatus, and a device. In the method, before model search and quantization, a plurality of single bit models are generated based on a to-be-quantized model, and evaluation parameters of layer structures in the plurality of single bit models are obtained. Further, after a candidate model selected from a candidate set is trained and tested, to obtain a target model, a quantization weight of each layer structure in the target model may be determined based on a network structure of the target model and evaluation parameters of all layer structures in the target model, a layer structure with a maximum quantization weight in the target model is quantized, and a model obtained through quantization is added to the candidate set.

A client computing device and a server computing device for federated machine learning. The client computing device is configured to receive a model comprising a set of common layers and a set of client-specific layers from the server computing device. After a training at the client computing device, the set of common layers and the set of client-specific layers are both updated. The set of updated common layers is sent to the server computing device, and the set of updated client-specific layers is stored at the client computing device. The server computing device is configured to receive multiple sets of updated common layers from different client computing devices.

A method, an apparatus, a computer device, a storage medium, and a program product for processing data are provided, which belong to the technical field of artificial intelligence. The method includes: acquiring model training information transmitted by each of at least two edge node devices, the model training information being transmitted in a form of plaintext, and being obtained by the edge node device by training sub-models through differential privacy; acquiring, based on the model training information transmitted by each of the at least two edge node devices, the sub-models trained by each of the at least two edge node devices; and performing, based on a target model ensemble policy, model ensemble on the sub-models trained by the at least two edge node devices, to obtain a global model. This solution expands the manner of model ensemble while ensuring the data security, thereby improving the model ensemble effect.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for parallelizing matrix operations. One of the methods includes implementing a neural network on a parallel processing device, the neural network comprising at least one sparse neural network layer, the sparse neural network layer being configured to receive an input matrix and perform matrix multiplication between the input matrix and a sparse weight matrix to generate an output matrix, the method comprising: for each row of the M rows of the output matrix, determining a plurality of tiles that each include one or more elements from the row; assigning, for each tile of each row, the tile to a respective one of a plurality of thread blocks of the parallel processing device; and computing, for each tile, respective values for each element in the tile using the respective thread block to which the tile was assigned.

A GHeT includes a bottom gate formed on a substrate; a first dielectric layer (DL) formed on the bottom gate; a monolayer film formed of an atomically thin material on the first DL; a bottom contact (BC) formed on part of the monolayer film; a second DL formed on the BC; a top contact (TC) formed on the second DL on top of the BC; a network of CNTs formed on the TC and the monolayer film, to define an overlap region with the monolayer film; a third DL formed on the CNT network, the monolayer film and the TC; and a top gate formed on the third DL and overlapping with the overlap region. Such GHeT design allows gate tunability of Gaussian peak position, height and width that define Gaussian transfer characteristic, thereby enabling simplified circuit architectures for various spiking neuron functions for emerging neuromorphic applications.

A semiconductor device that has low power consumption and is capable of performing a product-sum operation is provided. The semiconductor device includes first and second cells, a first circuit, and first to third wirings. Each of the first and second cells includes a capacitor, and a first terminal of each of the capacitors is electrically connected to the third wiring. Each of the first and second cells has a function of feeding a current based on a potential held at a second terminal of the capacitor, to a corresponding one of the first and second wirings. The first circuit is electrically connected to the first and second wirings and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wiring changes and accordingly the amount of current of the first wiring changes from I1 to I3 and the amount of current of the second wiring changes from I2 to I4, the first circuit generates a current with an amount I1-I2-I3+I4. Note that the potential of the third wiring is changed by firstly inputting a reference potential to the third wiring and then inputting a potential based on internal data or a potential based on information obtained by a sensor.

Disclosed are a network accuracy quantification method, system, and device, an electronic device and a readable medium, which are applicable to a many-core chip. The method includes: determining a reference accuracy according to a total core resource number of the many-core chip and the number of core resources required by each network to be quantified, with the number of the core resources required by each network to be quantified being the number of the core resources which is determined after each network to be quantified is quantified; and determining a target accuracy corresponding to each network to be quantified according to the reference accuracy and the total core resource number of the many-core chip.

Disclosed are a network accuracy quantification method, system, and device, an electronic device and a readable medium, which are applicable to a many-core chip. The method includes: determining a reference accuracy according to a total core resource number of the many-core chip and the number of core resources required by each network to be quantified, with the number of the core resources required by each network to be quantified being the number of the core resources which is determined after each network to be quantified is quantified; and determining a target accuracy corresponding to each network to be quantified according to the reference accuracy and the total core resource number of the many-core chip.

A device for implementing spike-timing-dependent plasticity is provided. The device includes a phase-change element, first and second electrodes disposed respective first and second surfaces of the phase-change element. The phase-change element includes a phase-change material with an inverse resistivity characteristic. The first electrode includes a first heater element, and a first electrical insulating layer which electrically insulates the first resistive heater element from the first electrode and the phase-change element. The second electrode includes a second resistive heater element, and a second electrical insulating layer which electrically insulates the second resistive heater element from the second electrode and the phase-change element.