G06N7/046

COGNITIVE MODELING APPARATUS FOR DETECTING AND ADJUSTING QUALITATIVE CONTEXTS ACROSS MULTIPLE DIMENSIONS FOR MULTIPLE ACTORS

The present design is directed to a system for detecting and adjusting qualitative contexts across multiple dimensions for multiple actors with cognitive computing techniques including a series of periodic execution components configured to operate over full or partial sets of received data, the series of periodic components comprising a peer to peer analyzer configured to detect anomalous behaviors among work-specific peer actors sharing similar types tasks, an actor behavior analyzer configured to examine change in an actor's behavior over time by comparing the similarity of past behavior and current behavior, a rate of change predictor configured to study changes in behavior over time for peer to peer performance according to the peer to peer analyzer, actor behavior change according to the actor behavior analyzer, and actor correlation analysis, and a semantic rule analyzer configured to encode conditional, provisional, cognitive, operational, and functional knowledge, and a plurality of signal managers.

Low entropy browsing history for content quasi-personalization
12158916 · 2024-12-03 · ·

The present disclosure provides systems and methods for content quasi-personalization or anonymized content retrieval via aggregated browsing history of a large plurality of devices, such as millions or billions of devices. A sparse matrix may be constructed from the aggregated browsing history, and dimensionally reduced, reducing entropy and providing anonymity for individual devices. Relevant content may be selected via quasi-personalized clusters representing similar browsing histories, without exposing individual device details to content providers.

Intelligent control with hierarchical stacked neural networks
09875440 · 2018-01-23 ·

A method of processing information is provided. The method involves receiving a message; processing the message with a trained artificial neural network based processor, having at least one set of outputs which represent information in a non-arbitrary organization of actions based on an architecture of the artificial neural network based processor and the training; representing as a noise vector at least one data pattern in the message which is incompletely represented in the non-arbitrary organization of actions; analyzing the noise vector distinctly from the trained artificial neural network; searching at least one database; and generating an output in dependence on said analyzing and said searching.

Efficient neural networks with elaborate matrix structures in machine learning environments
12165065 · 2024-12-10 · ·

A mechanism is described for facilitating slimming of neural networks in machine learning environments. A method includes learning a first neural network associated with machine learning processes to be performed by a processor of a computing device, where learning includes analyzing a plurality of channels associated with one or more layers of the first neural network. The method may further include computing a plurality of scaling factors to be associated with the plurality of channels such that each channel is assigned a scaling factor, wherein each scaling factor to indicate relevance of a corresponding channel within the first neural network. The method may further include pruning the first neural network into a second neural network by removing one or more channels of the plurality of channels having low relevance as indicated by one or more scaling factors of the plurality of scaling factors assigned to the one or more channels.

Compiler for optimizing number of cores used to implement neural network
12165069 · 2024-12-10 · ·

Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). The compiler of some embodiments receives a specification of a machine-trained network including multiple layers of computation nodes and generates a graph representing options for implementing the machine-trained network in the IC. In some embodiments, the graph includes nodes representing options for implementing each layer of the machine-trained network and edges between nodes for different layers representing different implementations that are compatible. In some embodiments, the graph is populated according to rules relating to memory use and the numbers of cores necessary to implement a particular layer of the machine trained network such that nodes for a particular layer, in some embodiments, represent fewer than all the possible groupings of sets of clusters.

Logic circuits with and-not gate for fast fuzzy decoders
09684873 · 2017-06-20 ·

A logic decoder circuit capable of performing Boolean or fuzzy logic has one or more logic components configured to perform a logic function of an AND-NOT gate, each AND-NOT gate comprising a circuit that performs a conjunction of an excitatory input X and an inhibitory input Y to obtain an output X-AND-NOT-Y substantially linearly for given ranges for X and Y. Certain preferred designs are provided for an X-AND-NOT-Y logic gate and a family of fast fuzzy decoders composed of such gates.

EFFICIENT NEURAL NETWORKS WITH ELABORATE MATRIX STRUCTURES IN MACHINE LEARNING ENVIRONMENTS
20250053814 · 2025-02-13 · ·

A mechanism is described for facilitating slimming of neural networks in machine learning environments. A method of embodiments, as described herein, includes learning a first neural network associated with machine learning processes to be performed by a processor of a computing device, where learning includes analyzing a plurality of channels associated with one or more layers of the first neural network. The method may further include computing a plurality of scaling factors to be associated with the plurality of channels such that each channel is assigned a scaling factor, wherein each scaling factor to indicate relevance of a corresponding channel within the first neural network. The method may further include pruning the first neural network into a second neural network by removing one or more channels of the plurality of channels having low relevance as indicated by one or more scaling factors of the plurality of scaling factors assigned to the one or more channels.

Hierarchical Fuzzy Controllers with Reduced Rule-Base

A waypoint, navigation controller and corresponding controlling methods are described, where the controller functions as a multiple input-multiple output, e.g., nonlinear angular velocity and linear speed controller for a land vessel such as a skid-steer vehicle. The controller and the controlling methods may be based on a fuzzy logic controller (alternatively referred to as fuzzy controller). The membership functions of the fuzzy controller may employ a trapezoidal structure with a symmetric rule-base. In addition, a Hierarchical Rule-Base Reduction (HRBR) is incorporated into the controller so as to select only the rules most influential on state errors by selecting inputs/outputs, determining the most globally influential inputs, and generating a hierarchy relating inputs via a Fuzzy Relations Control Strategy (FRCS). This disclosure is further directed to a fuzzy logic controller with Hierarchical Rule-Base Reduction (HRBR) and implemented as neural network and training of such a fuzzy logic controller via reinforcement learning based on an ANFIS actor.

Compiler for implementing gating functions for neural network configuration
12260317 · 2025-03-25 · ·

Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). The compiler of some embodiments receives a specification of a machine-trained network including multiple layers of computation nodes and generates a graph representing options for implementing the machine-trained network in the IC. In some embodiments, the compiler also generates instructions for gating operations. Gating operations, in some embodiments, include gating at multiple levels (e.g., gating of clusters, cores, or memory units). Gating operations conserve power in some embodiments by gating signals so that they do not reach the gated element or so that they are not propagated within the gated element. In some embodiments, a clock signal is gated such that a register that transmits data on a rising (or falling) edge of a clock signal is not triggered.

Artificial intelligence approaches for predicting conversion activity probability scores and key personas for target entities

The present disclosure relates to systems, methods, and non-transitory computer readable media for accurately and efficiently predicting conversion probability scores and key personas for target entities utilizing an artificial intelligence approach. For example, the disclosed systems utilize a conversion activity score neural network to predict conversion activity probability scores for target entities and utilize a persona prediction machine learning model to predict key personas associated with target entities. In particular, the disclosed systems utilize the conversion activity score neural network to generate a predicted conversion activity probability score for a target entity from input data including client device interactions of digital profiles belonging to the target entity as well as an entity feature vector representing characteristics of the target entity. The disclosed systems also (or alternatively) utilize a persona prediction machine learning model to determine a set of key personas for the target entity from the entity feature vector.