A display (100) comprising a plurality of LED chips (604), each LED chip (604) comprising a plurality of light emitting elements (606a-c). Each LED chip (604) is arranged such that a first light emitting element (606a) is configured to illuminate a sub-pixel, and a second light emitting element (606b) is configured to illuminate a sub-pixel using substantially the same wavelength of light as the first light emitting element. There is also described an LED chip, a display pixel, a controlling method, a computer device and a computer program for a display.

A display device includes a substrate, display units, and a plurality of integrated circuits (ICs). The substrate includes an active area and a non-active area. The non-active area is located around the active area. The display units are disposed in the active area of the substrate, and arranged in a matrix. The ICs are disposed in the active area of the substrate, arranged in a matrix, and are electrically coupled to the display units. Each of the ICs includes a shift register unit. Each of the shift register units of the ICs is configured to receive a previous-stage scan signal, and generate a current-stage scan signal according to the previous-stage scan signal. The ICs drive the display units according to the current-stage scan signals.

Disclosed herein is a driver integrated circuit (IC), which can be miniaturized and includes a plurality of circuits, including a first substrate, a first circuit driven at a first level voltage and mounted on the first substrate, a second substrate bonded to the first substrate, and a second circuit including one or more sub-circuits driven at a second level voltage that is higher than the first level voltage, wherein at least one among the one or more sub-circuits is mounted on the second substrate.

The present disclosure discloses a backlight apparatus for a display and a current control integrated circuit thereof. The backlight apparatus includes a backlight panel including light-emitting diode (LED) channels having a matrix structure and divided into a plurality of control units, a column driver configured to provide, in a horizontal period unit, column signals corresponding to columns of the LED channels, a row driver configured to provide, in a frame unit, row signals corresponding to rows of the LED channels and to sequentially provide the row signals in the horizontal period included in the frame, and current control integrated circuits disposed in the backlight panel in a way to correspond to the control units, respectively, and each configured to receive the column signal and the row signals corresponding to LED channels of the control unit and to control emission of the LED channels of the control unit.

Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.

A display device and an operating method of the display device are provided. The display device includes a first light emitting diode (LED), a first switch, a second switch, a second LED, a third switch, and a first controller. A first terminal of the first switch receives a first electrical signal. A first terminal of the second switch receives a second electrical signal. A first terminal of the third switch receives a third electrical signal. Here, whether the first switch, the second switch, and the third switch are switched on or off is determined by whether the first LED and the second LED are damaged or not. The first controller is configured to detect whether the first LED and the second LED are damaged or not, generate the second electrical signal and the electrical signal, and generate a plurality of control signals controlling the first switch to the third switch.

An illumination apparatus comprises a plurality of LEDs aligned to an array of directional optical elements wherein the LEDs are substantially at the input aperture of respective optical elements. An electrode array is formed on the array of optical elements to provide at least a first electrical connection to the array of LED elements. Advantageously such an arrangement provides low cost and high efficiency from the directional LED array.

A multiple graphics processing unit (GPU) based parallel graphics system comprising multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having an object division mode of operation. Each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem. According to the principles of the present invention, pixel (color and z depth) data buffered in the video memory of each GPU is communicated to the video memory of a primary GPU, and the video memory and the pixel processing subsystem in the primary GPU are used to carry out the image recomposition process, without the need for dedicated or specialized apparatus.

A display includes first and second pixel devices. The first pixel device includes a first control circuit and a first light emitting circuit. The first control circuit generates a first light emitting signal according to a first clock signal and a data signal during a first period. The first light emitting circuit emits light according to the first light emitting signal during second and third periods. The second pixel device includes a second control circuit and a second light emitting circuit. The second control circuit generates a second light emitting signal according to a second clock signal and the data signal during the second period. The second light emitting circuit is coupled to the second control circuit and emits light according to the second light emitting signal during the third period. The first period to the third period are arranged continuously in order.

A multiple graphics processing unit (GPU) based parallel graphics system comprising multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having an object division mode of operation. Each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem. According to the principles of the present invention, pixel (color and z depth) data buffered in the video memory of each GPU is communicated to the video memory of a primary GPU, and the video memory and the pixel processing subsystem in the primary GPU are used to carry out the image recomposition process, without the need for dedicated or specialized apparatus.