An electroluminescent display device comprises a pixel including a plurality of subpixels; a plurality of power lines for providing a power voltage to the plurality of subpixels; a data line for providing data signals to the plurality of subpixels; a plurality of gate lines for providing gate signals to the plurality of subpixels; and a reference node line for connecting a plurality of reference nodes included in the plurality of subpixels, wherein each of the subpixels comprises a light emitting diode and a subpixel driving circuit for controlling light emission of the light emitting diode, and wherein the subpixel driving circuit provides a driving current without including a high potential voltage to the light emitting diode as a reference voltage that is applied from one of the plurality of power lines to the reference node included in the subpixel driving circuit, and some of the plurality of subpixels include a compensation transistor connected to the reference node receiving the reference voltage.

Disclosed are a display substrate and a display device. A display region and a peripheral region are included. The peripheral region includes a plurality of shift registers and a plurality of clock signal lines. The plurality of clock signal lines are arranged side by side in a first direction and include a first clock signal line to a Zth clock signal line, Z≥1. The shift registers are connected with gate lines in the display region and the first clock signal line to the Zth clock signal line respectively. There is at least a group of ith clock signal lines satisfying that the ith clock signal lines include X ith clock signal lines which are arranged one by one according to a sequence of connection with shift registers and further include N ith clock signal lines.

An embodiment of the present disclosure provides a voltage converter including: an inductor in which a first electrode thereof receives an input voltage and a second electrode thereof is connected to a first node; a first transistor in which a first electrode thereof is connected to the first node and a second electrode thereof is connected to a second node providing an output voltage; a second transistor in which a first electrode thereof is connected to the first node and a second electrode thereof is connected to a reference terminal; and a current sensor connected to the first node and the second node, wherein the current sensor includes: a third transistor in which a first electrode thereof is connected to the first node and a second electrode thereof is connected to a third node; and a current mirror circuit that mirrors currents flowing through the second node, the third node, and a sensing terminal.

An embodiment of the present disclosure provides a voltage converter including: an inductor in which a first electrode thereof receives an input voltage and a second electrode thereof is connected to a first node; a first transistor in which a first electrode thereof is connected to the first node and a second electrode thereof is connected to a second node providing an output voltage; a second transistor in which a first electrode thereof is connected to the first node and a second electrode thereof is connected to a reference terminal; and a current sensor connected to the first node and the second node, wherein the current sensor includes: a third transistor in which a first electrode thereof is connected to the first node and a second electrode thereof is connected to a third node; and a current mirror circuit that mirrors currents flowing through the second node, the third node, and a sensing terminal.

A pixel arrangement structure provided by the present invention comprises a plurality of pixel groups. Each of the pixel groups comprises a first pixel, a second pixel, a third pixel, and a fourth pixel, wherein the first pixel includes a first sub-pixel and a second sub-pixel, and the second pixel includes the first sub-pixel and one second sub-pixel, two second sub-pixels in the first pixel and the second pixel share one same first sub-pixel, the third pixel and the fourth pixel both comprise a third sub-pixel and one second sub-pixel, two second sub-pixels in the third pixel and the fourth pixel share one same third sub-pixel, and the second sub-pixel is a blue sub-pixel. The invention increases the service lifespan of the blue sub-pixel.

A pixel arrangement structure provided by the present invention comprises a plurality of pixel groups. Each of the pixel groups comprises a first pixel, a second pixel, a third pixel, and a fourth pixel, wherein the first pixel includes a first sub-pixel and a second sub-pixel, and the second pixel includes the first sub-pixel and one second sub-pixel, two second sub-pixels in the first pixel and the second pixel share one same first sub-pixel, the third pixel and the fourth pixel both comprise a third sub-pixel and one second sub-pixel, two second sub-pixels in the third pixel and the fourth pixel share one same third sub-pixel, and the second sub-pixel is a blue sub-pixel. The invention increases the service lifespan of the blue sub-pixel.

The present application discloses a pixel driving circuit for a sub-pixel in light-emitting display. The pixel driving circuit includes a driving sub-circuit comprising N driving transistors connected in series. N is an integer greater than 1. The N driving transistors include a first driving transistor having a source electrode coupled to a first input voltage port and an N-th driving transistor having a drain electrode coupled to a light-emitting diode. Additionally, the pixel driving circuit includes a power-storage sub-circuit coupled to a gate electrode of the first driving transistor and the drain electrode of the N-th driving transistor. Furthermore, the pixel driving circuit includes a charge-input sub-circuit configured to use a first control signal from a first scan line to control a connection between the gate electrode of the first driving transistor and a data line supplying a data voltage.

A display device with high luminance is provided. A pixel includes a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor. One electrode of the light-emitting device is electrically connected to one of a source and a drain of the first transistor. A gate of the first transistor is electrically connected to one electrode of the first capacitor and one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is electrically connected to one electrode of the second capacitor. One electrode of the second capacitor is electrically connected to a first wiring having a function of supplying a first potential. The other electrode of the second capacitor is electrically connected to the other electrode of the first capacitor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor.

A gate driver includes at least one stage, which includes: a first output circuit configured to supply a voltage of a first power source or a voltage of a second power source to a first output terminal and including a fourth capacitor connected between a second node and the first output terminal; a second output circuit configured to supply a signal supplied to a fourth input terminal or the voltage of the second power source to a second output terminal; an input circuit configured to control a voltage of the second node and a voltage of a third node; a first signal processor configured to control a voltage of a first node; a second signal processor configured to control the voltage of the second node; and a third signal processor connected between the first node and the third node, and configured to control the voltage of the first node.

A gate driver includes at least one stage, which includes: a first output circuit configured to supply a voltage of a first power source or a voltage of a second power source to a first output terminal and including a fourth capacitor connected between a second node and the first output terminal; a second output circuit configured to supply a signal supplied to a fourth input terminal or the voltage of the second power source to a second output terminal; an input circuit configured to control a voltage of the second node and a voltage of a third node; a first signal processor configured to control a voltage of a first node; a second signal processor configured to control the voltage of the second node; and a third signal processor connected between the first node and the third node, and configured to control the voltage of the first node.