An display driver and an operating method of the display driver are provided. The display driver includes a receiver comprising a bias current control circuit. The receiver receives image data. The bias current control circuit computes a data bit rate of the image data, and adjusting a bias current of the receiver according to the data bit rate. The operating method is adapted to the display driver.

A display driving device and an anti-interference method thereof are provided. A timing controller outputs a data signal. A source driver detects an interference event according to the data signal, and outputs a feedback signal to the timing controller in response to the detection result of the interference event. The timing controller adjusts the signal strength of the data signal according to the feedback signal.

An display driver and an operating method of the display driver are provided. The display driver includes a receiver comprising a bias current control circuit. The receiver receives image data. The bias current control circuit computes a data bit rate of the image data, and adjusting a bias current of the receiver according to the data bit rate. The operating method is adapted to the display driver.

Embodiments disclosed herein relate to device and method for processing frames. For example, a buffer of a device is arranged to store a plurality of rendered frames rendered at a frame rendering rate and a time stamp for each of rendered frames. A compositor of a device is arranged to obtain a timestamp of a synchronisation signal for synchronising the display of frames with a display refresh rate. In response to obtaining a timestamp of a synchronisation signal, a compositor is arranged to trigger access to a buffer to obtain two rendered frames having timestamps closest to a timestamp of a synchronisation signal. An interpolator of a device is arranged to generate an interpolated rendered frame for display by performing an interpolation operation using two rendered frames. An interpolation operation takes into account the difference between timestamps of each of two rendered frames and a timestamp of a synchronisation signal.

A display device including: a timing controller configured to supply an adjustment option value through a data clock signal line during a first initialization period, and generate second data based on first data and a control signal and supply the second data through the data clock signal line during a data period; a data driver configured to generate an adjustment value based on the adjustment option value during the first initialization period, and generate third data based on the adjustment value and the second data and generate a data signal based on the third data during the data period; and a pixel configured to display an image based on the data signal.

A display apparatus may count a number of frames and adjust a cycle of clock training operations depending on a frame count number in a data-sensing driver to prevent or reduce unnecessary clock training operations. The data-sensing driver may perform more sensing operations by increasing the number of sensing operations and reducing the number of clock training operations. As a result, the data-sensing driver can quickly sense deterioration of a display panel of the display apparatus, and prevent or reduce a momentary afterimage, thereby improving a display quality.

In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

According to an embodiment, both the high-speed communication and the low-speed communication are performed using a single communication line, thereby reducing limitations on wiring on a PCB and increasing the utilization efficiency of a transmission line.

The present disclosure discloses a display apparatus having a lock function and a display driving circuit thereof. The display driving circuit of the present disclosure is configured to transfer a lock signal in a cascade way, receive a lock signal by pull-up and transfer the lock signal in an open drain form.

The present disclosure relates to a data transmission method, device, system, and display device. The method includes encoding clock training data to obtain two sets of encoded data corresponding to the clock training data and complementary to each other, sending a specified set of encoded data in the two sets of encoded data to a receiving end when positive and negative pins of the transmitting end and the receiving end are correspondingly connected, sending other set of coded data in the two sets of coded data than the specified set of encoded data to the receiving end when the positive and negative pins of the transmitting end and the receiving end are reversely connected. The receiving end may be configured to perform clock training according to the received encoded data.