Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

Disclosed herein are techniques to coordinate power management between a platform and a panel. Provided are apparatuses, techniques, and circuitry to determine whether to initiate power management features in a panel and send a signal from a platform to the panel including an indication that no frame updates are expected and power management functions can be initiated.

Disclosed herein are techniques to coordinate power management between a platform and a panel. Provided are apparatuses, techniques, and circuitry to determine whether to initiate power management features in a panel and send a signal from a platform to the panel including an indication that no frame updates are expected and power management functions can be initiated.

A display system modifies display cycles of one or more displays to perform a system operation while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods of the one or more displays such that blanking periods equal or exceed a blackout duration and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.

An electronic device is provided. The electronic device includes a memory, a display driver integrated circuit (DDIC), a display, and a processor that generates an image frame, transmits the image frame to the DDIC, and controls the DDIC to drive the display based on the image frame. The DDIC outputs a first timing signal at a first frame period, outputs a second timing signal at a second frame period longer than the first frame period when the reception of the image frame is delayed, and outputs a third timing signal at a third frame period longer than the first frame period and shorter than the second frame period when the image frame is not received for a designated reference time after the second timing signal is output.

In some examples, a method includes receiving, by a timing controller of a display device, an indication from an embedded controller of a computing device during a computing device startup procedure. In some examples, the method includes determining, by the timing controller, whether to access display image memory or computing device image memory based on the indication. In some examples, the method includes accessing, by the display device, the computing device image memory in response to determining to access the computing device image memory. In some examples, the method includes causing the display device to display an image from the computing device image memory in response to determining to access the computing device image memory.

A method, implemented by a computer system, and a system of organizing data of a wide area motion imagery frame and a method and a system of retrieving objects that match a user defined AOI from an image in a WAMI frame in a WAMI collection are described. The method of organizing includes dividing, by the computer system, an image of a WAMI frame into a plurality of tiles, each tile in the plurality of tiles comprising a plurality of pixels and having a pixel width and a pixel height; storing, by the computer system, the plurality of tiles as objects in an OSD, each object having an object identifier (OID); collecting, by the computer system, object identifiers (OIDs) of the objects; and storing, by the computer system, the OIDs in the OSD.

An image processing system comprises a first image processing device configured to process a frame of image data comprising a plurality of pixels, each having corresponding pixel values. Each of the pixel values include a first and second set of bits that may be separately or simultaneously accessed and/or processed. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may correspond to the width of a used data bus and/or features of a peripheral device connected to the image processor, such as a display.

An image processing system comprises a first image processing device configured to process a frame of image data comprising a plurality of pixels, each having corresponding pixel values. Each of the pixel values include a first and second set of bits that may be separately or simultaneously accessed and/or processed. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may correspond to the width of a used data bus and/or features of a peripheral device connected to the image processor, such as a display.