The present disclosure relates to a data transmission method, device, system, and display device. The method includes encoding clock training data to obtain two sets of encoded data corresponding to the clock training data and complementary to each other, sending a specified set of encoded data in the two sets of encoded data to a receiving end when positive and negative pins of the transmitting end and the receiving end are correspondingly connected, sending other set of coded data in the two sets of coded data than the specified set of encoded data to the receiving end when the positive and negative pins of the transmitting end and the receiving end are reversely connected. The receiving end may be configured to perform clock training according to the received encoded data.

The present disclosure relates to a data transmission method, device, system, and display device. The method includes encoding clock training data to obtain two sets of encoded data corresponding to the clock training data and complementary to each other, sending a specified set of encoded data in the two sets of encoded data to a receiving end when positive and negative pins of the transmitting end and the receiving end are correspondingly connected, sending other set of coded data in the two sets of coded data than the specified set of encoded data to the receiving end when the positive and negative pins of the transmitting end and the receiving end are reversely connected. The receiving end may be configured to perform clock training according to the received encoded data.

An electronic device, including a memory; a display panel; an image sensor disposed at a lower end of the display panel; a processor operatively connected to the image sensor; and a display driver integrated circuit operatively connected to the display panel and the processor, and configured to sense that a first frame is output on the display panel and to transmit a first signal to the processor based on the first frame being output on the display panel, wherein the processor is configured to: generate the first frame having a designated pixel value based on a shoot command being received from a user, control the display panel to output the first frame, and control the image sensor to capture an image based on the first signal being received from the display driver integrated circuit, and store the captured image in the memory.

When rendering a frame, e.g. that is to be used for rendering subsequent frames to be rendered, two versions of the frame are rendered, wherein the first version of the frame is rendered in its entirety but only a portion of the second version of the frame is rendered. The rendered portion of the second version of the frame is compared to a corresponding rendered portion of the first version of the frame. When the comparison determines that the two portions of the two versions match, the frame is, e.g. used for rendering subsequent frames, but when the comparison determines the two portions of the two versions do not match, an error operation is performed.

An image processor includes a frame buffer configured to collect an image data of pixels and configured to generate frame data, a display controller configured to generate the frame update command based on a vertical synchronizing signal and a frame per second signal representing a number of activating of the frame update signal in a second and an operating part configured to generate the vertical synchronizing signal and the image data. When the frame data is generated, the frame buffer activates a frame update signal in response to a frame update command and outputs the frame data. When the frame per second signal is less than a predetermined threshold voltage, the operating part sets a lower limit of a range of a frequency to a predetermined minimum frequency.

An image processor includes a frame buffer configured to collect an image data of pixels and configured to generate frame data, a display controller configured to generate the frame update command based on a vertical synchronizing signal and a frame per second signal representing a number of activating of the frame update signal in a second and an operating part configured to generate the vertical synchronizing signal and the image data. When the frame data is generated, the frame buffer activates a frame update signal in response to a frame update command and outputs the frame data. When the frame per second signal is less than a predetermined threshold voltage, the operating part sets a lower limit of a range of a frequency to a predetermined minimum frequency.

A backlight control device adapted to control a plurality of backlight sources is provided. The backlight control device includes a timing control circuitry and a local-dimming control circuitry. The timing control circuitry is configured to generate a transmission packet according to a first customized content specification, where the transmission packet includes control information and brightness information. The timing control circuitry includes a differential circuit, where the differential circuit is configured to transmit the transmission packet according to a differential voltage level. The local-dimming control circuitry includes a receiving circuit electrically coupled to the differential circuit. The receiving circuit is configured to receive the transmission packet. The local-dimming control circuitry is configured to transmit a light source control signal according to the control information and the brightness information.

A backlight control device adapted to control a plurality of backlight sources is provided. The backlight control device includes a timing control circuitry and a local-dimming control circuitry. The timing control circuitry is configured to generate a transmission packet according to a first customized content specification, where the transmission packet includes control information and brightness information. The timing control circuitry includes a differential circuit, where the differential circuit is configured to transmit the transmission packet according to a differential voltage level. The local-dimming control circuitry includes a receiving circuit electrically coupled to the differential circuit. The receiving circuit is configured to receive the transmission packet. The local-dimming control circuitry is configured to transmit a light source control signal according to the control information and the brightness information.

The present teaching relates to method, system, medium, and implementations for LED display. A first signal is received that signals a timing for a next data transfer. In response to the first signal, a bit-based image block stored in a memory is transferred, via a bus connected thereto, to one of a pair of alternate buffers pointed to by a write buffer pointer, which is subsequently toggled to point to another of the pair of alternate buffers. A second signal is received that signals a timing for refreshing the LED display. In response to the second signal, the bit-based image block is retrieved from the one of the pair of alternate buffers pointed to by a read buffer pointer, which is then toggled to point to the other of the pair of alternate buffers. The lights of the LED display are then refreshed in accordance with control signals generated based on the bit-based image block.

The present teaching relates to method, system, medium, and implementations for LED display. A first signal is received that signals a timing for a next data transfer. In response to the first signal, a bit-based image block stored in a memory is transferred, via a bus connected thereto, to one of a pair of alternate buffers pointed to by a write buffer pointer, which is subsequently toggled to point to another of the pair of alternate buffers. A second signal is received that signals a timing for refreshing the LED display. In response to the second signal, the bit-based image block is retrieved from the one of the pair of alternate buffers pointed to by a read buffer pointer, which is then toggled to point to the other of the pair of alternate buffers. The lights of the LED display are then refreshed in accordance with control signals generated based on the bit-based image block.