A video display method includes: acquiring at least one frame image corresponding to a current display time point in at least one source video; reading a stage configuration file, obtaining a stage modeling parameter of the stage space at the current display time point and a corresponding relationship between the at least one frame image and the stage space according to a specific stage related parameter in the stage configuration file; according to the stage modeling parameter and the corresponding relationship, processing the at least one frame image to obtain divided regions corresponding to all display screens included in the at least one stage plane; determining display contents corresponding to the divided regions, and copying the display contents to at least one target memory; and outputting a content in the at least one target memory to the at least one stage plane for display.

A video display method includes: acquiring at least one frame image corresponding to a current display time point in at least one source video; reading a stage configuration file, obtaining a stage modeling parameter of the stage space at the current display time point and a corresponding relationship between the at least one frame image and the stage space according to a specific stage related parameter in the stage configuration file; according to the stage modeling parameter and the corresponding relationship, processing the at least one frame image to obtain divided regions corresponding to all display screens included in the at least one stage plane; determining display contents corresponding to the divided regions, and copying the display contents to at least one target memory; and outputting a content in the at least one target memory to the at least one stage plane for display.

An image processor includes a frame buffer configured to collect an image data of pixels and configured to generate frame data, a display controller configured to generate the frame update command based on a vertical synchronizing signal and a frame per second signal representing a number of activating of the frame update signal in a second and an operating part configured to generate the vertical synchronizing signal and the image data. When the frame data is generated, the frame buffer activates a frame update signal in response to a frame update command and outputs the frame data. When the frame per second signal is less than a predetermined threshold voltage, the operating part sets a lower limit of a range of a frequency to a predetermined minimum frequency.

An image processor includes a frame buffer configured to collect an image data of pixels and configured to generate frame data, a display controller configured to generate the frame update command based on a vertical synchronizing signal and a frame per second signal representing a number of activating of the frame update signal in a second and an operating part configured to generate the vertical synchronizing signal and the image data. When the frame data is generated, the frame buffer activates a frame update signal in response to a frame update command and outputs the frame data. When the frame per second signal is less than a predetermined threshold voltage, the operating part sets a lower limit of a range of a frequency to a predetermined minimum frequency.

The present teaching relates to method, system, medium, and implementations for LED display. A first signal is received that signals a timing for a next data transfer. In response to the first signal, a bit-based image block stored in a memory is transferred, via a bus connected thereto, to one of a pair of alternate buffers pointed to by a write buffer pointer, which is subsequently toggled to point to another of the pair of alternate buffers. A second signal is received that signals a timing for refreshing the LED display. In response to the second signal, the bit-based image block is retrieved from the one of the pair of alternate buffers pointed to by a read buffer pointer, which is then toggled to point to the other of the pair of alternate buffers. The lights of the LED display are then refreshed in accordance with control signals generated based on the bit-based image block.

The present teaching relates to method, system, medium, and implementations for LED display. A first signal is received that signals a timing for a next data transfer. In response to the first signal, a bit-based image block stored in a memory is transferred, via a bus connected thereto, to one of a pair of alternate buffers pointed to by a write buffer pointer, which is subsequently toggled to point to another of the pair of alternate buffers. A second signal is received that signals a timing for refreshing the LED display. In response to the second signal, the bit-based image block is retrieved from the one of the pair of alternate buffers pointed to by a read buffer pointer, which is then toggled to point to the other of the pair of alternate buffers. The lights of the LED display are then refreshed in accordance with control signals generated based on the bit-based image block.

This disclosure provides methods, devices, and systems for data synchronization. The present implementations more specifically relate to adjusting a rate at which display updates are output to a digital display based on an activity level associated with the digital display. For example, digital displays that render images with relatively little motion or user engagement may be associated with lower activity levels, whereas digital displays that render images with more significant motion or user engagement may be associated with higher activity levels. In some aspects, an adaptive display interface may dynamically increase the rate at which display frames are output to a display when the activity level increases and may dynamically decrease the rate at which display frames are output to the display when the activity level decreases.

A device for controlling a data interface of a display apparatus, can include a timing controller to encode one data transfer packet including image data according to a pixel clock to output the one data transfer packet to an interface line, and a source driver to decode the one data transfer packet to recover the image data. Also, the image data includes first image data of a first color and second image data of a second color between a first delimiter signal having a first logic value and a second delimiter signal having a second logic value, a most significant bit of the first image data is closer to the first delimiter signal than a least significant bit of the first image data, and a most significant bit of the second image data is closer to the second delimiter signal than a least significant bit of the second image.

A device for controlling a data interface of a display apparatus, can include a timing controller to encode one data transfer packet including image data according to a pixel clock to output the one data transfer packet to an interface line, and a source driver to decode the one data transfer packet to recover the image data. Also, the image data includes first image data of a first color and second image data of a second color between a first delimiter signal having a first logic value and a second delimiter signal having a second logic value, a most significant bit of the first image data is closer to the first delimiter signal than a least significant bit of the first image data, and a most significant bit of the second image data is closer to the second delimiter signal than a least significant bit of the second image.

A display driving device according to the present disclosure capable of changing image data at a different time for each color when the image data is changed includes: a first array composed of sampling latches configured to latch n-bit image data for each channel; a second array composed of holding latches configured to latch the image data latched in the sampling latches at a latch timing determined for each latch group; a signal generation circuit configured to generate a latch enable signal which causes the holding latches to perform a latch operation at the latch timing determined for each latch group; and a third array including level shifters configured to shift a voltage level of the image data output from the holding latches.