The present technology relates to an image processing apparatus, an image processing method, and a program that a memory capacity necessary for deformation processing of each frame image of a moving image can be reduced. Pixel data of a first frame image being each frame image of an input moving image is written into a predetermined plurality of storage areas in a storage unit in a predetermined write-in order, and the pixel data of the first frame image written into the storage unit is reads out in a predetermined read-out order, thereby generating a second frame image being the first frame image deformed. The write-in of the pixel data and the read-out of the pixel data are performed in parallel, the first frame image is divided into blocks in 2 rows×2 columns or more, the blocks are written into each of the storage area one by one, and the block to be written next is written into the storage area that becomes vacant by reading out the pixel data immediately before. The present technology is applicable, for example, to an image processing apparatus.

A processing method and device for multi-screen splicing display are disclosed. The method includes: receiving instruction information for multi-screen splicing display, where the instruction information is used to instruct to splice at least two physical display screens for display; sending, according to the instruction information, display data to a video RAM of a virtual display screen formed by splicing the at least two physical display screens, where a size of the video RAM of the virtual display screen corresponds to a size of the virtual display screen; dividing the display data into at least two data blocks that correspond to sizes of the at least two physical display screens, and respectively sending the data blocks obtained by division to video RAMs of corresponding physical display screens.

Techniques for selective display frame fetching can include receiving or fetching rendered display frames by a display engine. The display engine can obtain an indication of a new frame and, in response to the indication of the new frame not including an indication of a flip completion event: (i) fill the display buffer with the new frame; (ii) scan out the new frame from the display buffer to a display port; and (iii) apply an adaptive contrast and backlight enhancement based on a histogram of changes in the new frame.

Techniques for selective display frame fetching can include receiving or fetching rendered display frames by a display engine. The display engine can obtain an indication of a new frame and, in response to the indication of the new frame not including an indication of a flip completion event: (i) fill the display buffer with the new frame; (ii) scan out the new frame from the display buffer to a display port; and (iii) apply an adaptive contrast and backlight enhancement based on a histogram of changes in the new frame.

The present teaching relates to method, system, medium, and implementations for LED display. A first signal is received that signals a timing for a next data transfer. In response to the first signal, a bit-based image block stored in a memory is transferred, via a bus connected thereto, to one of a pair of alternate buffers pointed to by a write buffer pointer, which is subsequently toggled to point to another of the pair of alternate buffers. A second signal is received that signals a timing for refreshing the LED display. In response to the second signal, the bit-based image block is retrieved from the one of the pair of alternate buffers pointed to by a read buffer pointer, which is then toggled to point to the other of the pair of alternate buffers. The lights of the LED display are then refreshed in accordance with control signals generated based on the bit-based image block.

The present teaching relates to method, system, medium, and implementations for LED display. A first signal is received that signals a timing for a next data transfer. In response to the first signal, a bit-based image block stored in a memory is transferred, via a bus connected thereto, to one of a pair of alternate buffers pointed to by a write buffer pointer, which is subsequently toggled to point to another of the pair of alternate buffers. A second signal is received that signals a timing for refreshing the LED display. In response to the second signal, the bit-based image block is retrieved from the one of the pair of alternate buffers pointed to by a read buffer pointer, which is then toggled to point to the other of the pair of alternate buffers. The lights of the LED display are then refreshed in accordance with control signals generated based on the bit-based image block.

The present teaching relates to method, system, medium, and implementations for data transfer in LED display. A signal signaling a timing for a next data transfer is received. In response to the signal, a next data transfer instruction is obtained that instructs reading a bit-based image block of an image from a memory. The bit-based image block is transferred, according to the next data transfer instruction, from the memory via a bus connected thereto, to one of a pair of alternate buffers pointed to by a write buffer pointer. Then, the write buffer pointer is toggled to point to another of the pair of alternate buffers and the process repeats. The bit-based image blocks alternately stored in the buffers are later retrieved and displayed on the LED display.

The present teaching relates to method, system, medium, and implementations for data transfer in LED display. A signal signaling a timing for a next data transfer is received. In response to the signal, a next data transfer instruction is obtained that instructs reading a bit-based image block of an image from a memory. The bit-based image block is transferred, according to the next data transfer instruction, from the memory via a bus connected thereto, to one of a pair of alternate buffers pointed to by a write buffer pointer. Then, the write buffer pointer is toggled to point to another of the pair of alternate buffers and the process repeats. The bit-based image blocks alternately stored in the buffers are later retrieved and displayed on the LED display.

Displays and display driving methods implement a pixel set/reset scheme. Pixel cells of an example display each include a set terminal, a reset terminal, an output terminal, and a set/reset circuit. Responsive to receiving a set signal on the set terminal, the set/reset circuit asserts a first signal on the output terminal and maintains the first signal on the output terminal until a reset signal is received on the reset terminal. Responsive to receiving a reset signal on the reset terminal, the set/reset circuit asserts a second signal on the output terminal and maintains the second signal on the output terminal until a set signal is received on the set terminal. The optical output of the pixel depends on when the first signal and the second signal are asserted on the output terminal of the set/reset circuit during a predefined modulation period.

System and method of dynamically adjusting a frame buffer resolution. An average frame rate is dynamically computed based on the frame rates with respect to rendering a sequence of previous frames to a frame buffer. The frame rates may vary with the processing load of an associated graphics processor. A target scaling factor for frame buffer resolution is computed based upon the dynamic average frame rate and a desired frame rate. The current scaling factor of frame buffer resolution for rendering a respective frame data of a sequence of frame data to the frame buffer is adjusted incrementally to reach the target scaling factor. Accordingly, frame resolutions for rendering the sequence of frame data to the frame buffer are incrementally adjusted based on corresponding current scaling factors.