Techniques for selective display frame fetching are disclosed. Some example techniques disclosed herein cause at least one processor to at least determine if an indication of a new frame includes an indication of a flip event, and identify one or more dirty regions of the new frame based on the flip event. Disclosed example techniques also cause the at least one processor to fill a display buffer with the one or more dirty regions of the new frame, scan out the one or more dirty regions of the new frame from the display buffer to a display port, and apply an adaptive contrast and backlight enhancement based on a histogram of changes in the new frame.

Techniques for selective display frame fetching are disclosed. Some example techniques disclosed herein cause at least one processor to at least determine if an indication of a new frame includes an indication of a flip event, and identify one or more dirty regions of the new frame based on the flip event. Disclosed example techniques also cause the at least one processor to fill a display buffer with the one or more dirty regions of the new frame, scan out the one or more dirty regions of the new frame from the display buffer to a display port, and apply an adaptive contrast and backlight enhancement based on a histogram of changes in the new frame.

A control method for display switching, an electronic device, and a storage medium are provided. The control method for display switching includes: establishing a first buffer and a second buffer at a kernel layer and initializing the first buffer; establishing a first service process and a second service process at a user layer, and controlling the first service process to render a first image according to a display parameter of a first buffer and transmit it to a display screen via the first buffer for display; and initializing the second buffer according to a switching instruction, and controlling the second service process to render a second image according to a display parameter of the second buffer and transmit it to the display screen via the second buffer so as to make the display screen switch to displaying the second image.

A video processor chip includes a memory circuit, a frame rate converter circuit, and an image compensation circuit. The memory circuit includes first to third storage spaces. The frame rate converter circuit sequentially writes multiple frame data in video data to the first to the third storage spaces respectively, and reads second data in the frame data from the memory circuit to perform a frame rate conversion when first data in the frame data is written to the memory circuit. The second data is a previous frame data of the first data. The image compensation circuit reads third data in the frame data from the memory circuit when the frame rate converter circuit reads the second data, and performs an image compensation according to a difference between the second data and the third data. The third data is a previous frame data of the second data.

An electronic device according to various embodiments may include: a housing; a display panel exposed through part of the housing; a display driver Integrated Circuit (IC) for driving the display panel; a processor located inside the housing and operatively coupled to the display panel and the display driver IC; and a memory located inside the housing and operatively coupled to the processor and the display driver IC. The memory may store instructions, when executed, causing the processor to display a first screen through the display panel, identify whether there is a request for entering a low power state, generate information on a second screen including at least part of the first screen and write the information in the memory, in response to the request for entering the low power state, enter the low power state in response to writing the information, and causing the display driver IC to display the second screen through the display panel, based on the information, written in the memory, on the second screen, while the processor is in the low power state.

An electronic display may include a pixel circuit. The pixel circuit may include memory storage to store data values representative of image data to be depicted via the pixel circuit. The memory storage may also include memory components for storing bits of the data value. The pixel circuit may also include a light-emitting device for emitting light based at least in part on the data value and a controller. The controller may receive the data value and store the bits based on a mapping between the bits and the memory components. The mapping may be determined based on routing one or more of the bits associated with one or more defective memory components of the memory components to one or more other memory components of the memory components. The controller may also drive the light-emitting device to emit light based on the bits stored in accordance with the mapping.

An electronic display may include a pixel circuit. The pixel circuit may include memory storage to store data values representative of image data to be depicted via the pixel circuit. The memory storage may also include memory components for storing bits of the data value. The pixel circuit may also include a light-emitting device for emitting light based at least in part on the data value and a controller. The controller may receive the data value and store the bits based on a mapping between the bits and the memory components. The mapping may be determined based on routing one or more of the bits associated with one or more defective memory components of the memory components to one or more other memory components of the memory components. The controller may also drive the light-emitting device to emit light based on the bits stored in accordance with the mapping.

A processing system reduces latency and improves predictability of a scan out position to support graphics processing unit (GPU) front buffer rendering with a variable refresh rate (VRR) display. The GPU detects whether front buffer rendering such as inking is occurring on a frame-by-frame basis. In order to maintain a safe distance from the current scan out position and achieve low latency to improve the user experience, the GPU increases the refresh rate of the VRR display to a low-latency (high-frequency) fixed refresh rate in response to detecting front buffer rendering. In some embodiments, the GPU decreases the refresh rate in response to detecting a static screen to save power.

A processing system reduces latency and improves predictability of a scan out position to support graphics processing unit (GPU) front buffer rendering with a variable refresh rate (VRR) display. The GPU detects whether front buffer rendering such as inking is occurring on a frame-by-frame basis. In order to maintain a safe distance from the current scan out position and achieve low latency to improve the user experience, the GPU increases the refresh rate of the VRR display to a low-latency (high-frequency) fixed refresh rate in response to detecting front buffer rendering. In some embodiments, the GPU decreases the refresh rate in response to detecting a static screen to save power.

Methods and systems for multiple-buffered display rendering without the use of hardware or software interrupts. In a first repeating process, a processor writes data for a frame a selected frame buffer and, upon completion of the frame, a swap buffer signal is transmitted. In response to the swap buffer signal, the GPU updates a memory register of the display controller to indicate that the selected frame buffer can be used in the next display synchronization interval. In a separate repeating process, the display controller monitors memory register and, in a display synchronization interval, identifies the frame buffer to use for display.