Disclosed is a display substrate, including: a base including a display region and a peripheral region; sub-pixels in the display region; data lines in at least the display region and extending in a first direction and electrically connected to the sub-pixels gate lines in at least the display region and extending in a second direction intersecting with the first direction electrically connected to the sub-pixels pads in the peripheral region; data leads in the peripheral region and electrically connected to the data lines and the pads; a gate driver circuit in the peripheral region and electrically connected to the gate lines; gate drive lines in the peripheral region and electrically connected to the gate driver circuit; gate leads in the peripheral region and extending in the first direction, which are electrically connected to the gate drive lines and the pads and located between the data leads.

A display device includes a substrate, one or more scan stages disposed on the substrate, a first conductive layer disposed on the substrate, and scan control lines electrically connected to each of the one or more scan stages, a first organic insulating layer disposed on the first conductive layer, and a second organic insulating layer disposed on the first organic insulating layer. The first organic insulating layer and the second organic insulating layer overlap the scan control lines.

A shift register, a driving method therefor, a gate driving circuit and a display device. The shift register comprises: an input module, a first reset module, a second reset module, an output module. The input module is configured to write input signal of a signal input terminal STU into second node Q2 through second clock signal terminal CLKB, and to connect Q2 with first node Q1 through STU. The first reset module is configured to write signal of first direct current signal terminal into third node Q3 through STU, and to write reset signal of reset signal terminal STD into Q3 and connect Q2 with Q1 through STD. The second reset module is configured to write a signal of the first direct current signal terminal into a signal output terminal OUT through Q3. The output module is configured to write a first clock signal of CLKA into OUT through Q1.

The present disclosure relates to a display structure, a display panel including the display structure, and a display device including the display panel and an image acquisition device. The display structure includes a plurality of pixels disposed in a first region of the display structure, wherein each pixel of the plurality of pixels includes a plurality of sub-pixels of N number of colors, and each sub-pixel of the plurality of sub-pixels includes an organic light emitting diode; and N number of driving circuits disposed in a second region of the display structure, wherein an i.sup.th driving circuit of the N number of driving circuits is configured to drive each sub-pixel of an i.sup.th color of the plurality of sub-pixels, wherein 1≤i≤N and N is an integer greater than 1.

A gate driver circuit, a display device and a driving method. The gate driver circuit includes: a scan signal generation circuit, wherein the scan signal generation circuit includes N1 stages of first output terminals, and the scan signal generation circuit is configured to output N1 first pulse scan signals stage by stage respectively through the N1 stages of first output terminals; and N2 level conversion circuits, wherein the N2 level conversion circuits are configured to output under a control of a plurality of conversion control signals N1 second pulse scan signals which are in one-to-one correspondence with the N1 first pulse scan signals, and the plurality of conversion control signals include a plurality of first sub-control signals which are the N1 first pulse scan signals, wherein N1 is an integer greater than or equal to 2, and N2 is an integer greater than or equal to 2.

A display apparatus includes a display panel displaying an image based on input image data, a driving controller determining a low frequency driving mode and a normal driving mode based on the input image data, a gate driver outputting a gate signal, a data driver outputting a data voltage, and a power voltage generator outputting power voltages. The driving controller is configured to generate a writing frame in which data is written in a pixel of the display panel and a holding frame in which the written data is maintained without writing data in the pixel in the low frequency driving mode. The driving controller is configured to operate at least one of the driving controller, the data driver, and the power voltage generator in a power reducing mode during the holding frame.

The present disclosure provides a shift register, a drive method thereof, and a gate drive circuit. The shift register includes an input circuit, a reset circuit, a first output circuit, and a second output circuit. The input circuit is configured to provide an input signal from an input terminal to a first node. The reset circuit is configured to provide a first voltage from a first voltage terminal to the first node under the control of a reset signal from a reset signal terminal. The first output circuit is configured to output from a first output terminal one of a first clock signal and a second clock signal as a first scan signal. The second output circuit is configured to output from a second output terminal the other of the first clock signal and the second clock signal as a second scan signal.

A display apparatus includes a display area, a non-display area surrounding the display area, and a bending area formed in at least one side of the non-display area. The display apparatus includes a first glass substrate provided in the display area, a second glass substrate provided in the non-display area, an anti-etching member provided to overlap the bending area, and a link line portion formed on the anti-etching member and formed to overlap the non-display area.

A driving method of a display panel is provided, by pre-storing a new setting information of a source output enable signal in a peer-to-peer protocol, and detecting a default setting information of the source output enable signal, and according to a detection result of the default setting information, invoking the new setting information when switching different drivers, a setting information of the source output enable signal in the peer-to-peer protocol can be unified, thereby avoiding the charging time difference due to a replacement of drivers.

A shifting register, a driving method thereof, a driving circuit and a display device are provided. The shifting register includes a control circuit (10), a first output circuit (20), a second output circuit (30) and a first switching transistor (T1). Shifting output of signals may be realized through interaction of all of the circuits. Moreover, an influence of a leak current on a signal of a second end of the first switching transistor is reduced by setting the first switching transistor (T1) to isolate the second output circuit (30) and a second node (N2).