A scan driving circuit and a display panel include an even number of signal wires divided into an odd group of signal wires and an even group of signal wires; and a plurality of scanning sub-circuits, each scanning sub-circuit including an assembly coupled between the odd group of signal wires and the even group of signal wires and including a register part and a pull-down part, and a load coupled between the register part and the pull-down part; wherein the register parts and the pull-down parts that are configured on a same side of the loads are alternately arranged, and any two of the register parts that are separated by N of the scanning sub-circuits and configured on one side of the loads are cascaded with each other, wherein N is half of a total number of the even number of signal wires.

Disclosed are a display panel and a display device. The display panel includes a display area, a plurality of light-emitting elements located in the display area, and at least one driver circuit located in the display area; the plurality of light-emitting elements includes a plurality of light-emitting element rows extend in a first direction and arranged in a second direction, where the first direction and the second direction intersect; the at least one driver circuit includes a plurality of shift register circuits disposed in cascade and a shift register circuit of the plurality of shift register circuits is located between adjacent light-emitting element rows of the plurality of light-emitting element rows.

An array substrate has a display area and a peripheral area located outside the display area. The display area includes two first sides that are substantially parallel and arc sides connected to ends of the first sides. The array substrate includes at least one gate driving circuit. Each gate driving circuit includes GOA units sequentially distributed along each arc side in at least one arc side and active GOA units sequentially distributed along a first side connected to the arc side. The GOA units includes at least one active GOA unit and at least one dummy GOA unit. Each active GOA unit is configured to provide a driving signal to at least one sub-pixel. A distance between two adjacent GOA units in the GOA units is approximately same as a distance between two adjacent active GOA units in the active GOA units.

There is provided a gate driving circuit including cascaded Gate Driver On Array (GOA) units, each GOA unit drives a row of pixels and includes a starting sub-unit, an output sub-unit and an output terminal, in the GOA unit at a first stage, the starting sub-unit is coupled with a starting signal, a first control signal, a second control signal and a constant voltage potential, and the output sub-unit is coupled with a first clock signal and a first power supply signal; in the GOA unit at an n.sup.th stage, the starting sub-unit is coupled with the starting signal, the first control signal, the second control signal and the output terminal of the GOA unit at an (n−1).sup.th stage, the output sub-unit is coupled with the first power supply signal and the output terminal of the GOA unit at an (n+1).sup.th stage, n is an integer greater than 1.

Discussed is a display device including a substrate, semiconductor light-emitting elements on the substrate, flip-flops which can apply an electrical signal to the semiconductor light-emitting elements to maintain the semiconductor light-emitting elements in a light-emitting state for a predetermined time interval, scan electrodes and data electrodes electrically connected to the flip-flops, respectively, and a driver. When a frame synchronization signal is generated during a time interval from a time point of the generation of a sub field signal to a time point of the generation of a subsequent sub field signal, the driver can prevent a voltage from being applied to the data electrodes for the time interval.

A gate driver on array (GOA) circuit and a display panel are provided. The GOA circuit includes a plurality of cascaded GOA units. The GOA units include a first GOA unit and a second GOA unit. By setting a virtual reset module in the second GOA unit, and the virtual reset module corresponding to the reset module in the first GOA unit, a difference between the first GOA unit and the second GOA unit is reduced and stability of the GOA circuit is improved.

An embodiment of the present disclosure provides an array substrate having a display area and a peripheral area surrounding the display area, the display area is provided with display units therein, the display area includes a curved edge, the peripheral area is provided therein with a plurality of shift register units cascaded, at positions corresponding to the curved edge of the display area, an extending direction in which a first edge of each shift register unit extends is parallel to an outer tangent line of the curved edge or is consistent with an extending direction in which the curved edge extends, and the first edge is an inner edge of each shift register unit close to the curved edge.

Embodiments of the present invention disclose an array substrate and a display panel. The array substrate includes a first substrate, and a first metal layer, a second metal layer, and a first shielding line sequentially disposed on the first substrate. The first metal layer includes a plurality of scan lines, the second metal layer includes a signal transmission line electrically connected to all of the scan lines, and at least a part of an orthographic projection of a wiring part of the signal transmission line on the first substrate coincides with an orthographic projection of the first shielding line on the first substrate.

The present disclosure provides a display substrate, a method for manufacturing the same, a driving method and a display device. The display substrate includes a base substrate, gate lines, data lines and sub-pixels. The sub-pixels include sub-pixel columns corresponding to the data lines in a one-to-one manner. In a sub-pixel driving circuit of the sub-pixel, a driving transistor and a data writing transistor are located at a first side of an aperture area of the sub-pixel; a sensing transistor is located at a second side of the aperture area of the sub-pixel. The first side and the second side are opposite sides of the aperture area along the extension direction of the data lines. Gate electrodes of sensing transistors in a same sub-pixel row, and gate electrodes of data writing transistors in an adjacent next sub-pixel row, are all coupled to a gate line corresponding to the adjacent next sub-pixel row. There is a first overlapping area between an orthographic projection of a first electrode plate of the storage capacitor to the base substrate and an orthographic projection of a second electrode plate of the storage capacitor to the base substrate; an orthographic projection of the first overlapping area to the base substrate at least partially overlaps an orthographic projection of the corresponding aperture area of the sub-pixel.

Disclosed are a drive circuit, an array substrate and a display panel. The first signal line is for receiving and transmitting the first reset control signal after the display of the current frame ends. First ends of the first thin film transistor and the second thin film transistor are connected to the first signal line. Second ends of the first thin film transistor and the second thin film transistor are connected to the second signal line. Third ends of the first thin film transistor and the second thin film transistor are connected to the controlled end and output end of the output module, respectively. The first thin film transistor and the second thin film transistor are for outputting the DC signal to the controlled end and the output end of the output module, respectively, upon receiving the first reset control signal, to reset the output module.