A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.

A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.

Provided is a display panel including a main display area, a component area having a transmissive area, a peripheral area outside the main display area, a substrate, a bottom metal layer on the substrate, and defining an opening corresponding to the transmissive area, a valley portion adjacent to a boundary between the bottom metal layer and the transmissive area, and a thin-film encapsulation layer on the valley portion, and including an inorganic layer and an organic layer.

A shift register unit and a driving method thereof, a gate driving circuit, and a display device are provided. In the shift register unit, the input circuit inputs an input signal to a first node; the output circuit outputs an output signal to an output terminal; the first control circuit performs a first control on a level of a first control node; the first noise reduction control circuit controls a level of a second node; the second control circuit performs a second control on a level of a second control node; the second noise reduction control circuit controls a level of a third node; the first voltage-stabilizing circuit performs a third control on the level of the second control node, and the second control and the third control cause at least part of the second noise reduction control circuit to be in different bias states.

A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.

The present application provides a GOA circuit and a display panel. In the GOA circuit, one of two GOA units of a same stage in GOA sub circuits at left and right sides of the display panel is deployed only with an all-on module and the other one of the two GOA units is deployed only with an all-off module. In such a way, both the number of the all-on modules and the number of the all-off modules required in the GOA unit are halved, thereby reducing the area occupied by the GOA circuit. It is beneficial for realizing a display panel with a narrow bezel.

A thin-film transistor (TFT) array substrate is provided. The TFT array substrate is structured to change the way that sub-pixels are arranged so that during a displaying period of a frame of image, the sub-pixels that have inconsistent brightness/darkness become alternate with each other spatially so that a displaying defect of vertical bright/dark lines can be improved and the overall resistance of the data line can be reduced to thereby reduce resistance-capacitance delay and prevent incorrect charging at a tail end of a scan line or a data line.

An electro-optical device includes one or more control lines that include a scanning line, a data line and a pixel circuit. The pixel circuit has a drive transistor, a write-in transistor with a gate which is electrically connected to the scanning line, a light-emitting element that emits light at a brightness that depends on the size of a current that is supplied through the drive transistor, and a control line which overlaps the gate of the drive transistor when viewed from a direction that is perpendicular to a surface of a substrate on which the pixel circuit is formed is included in the one or more control lines.

The present disclosure relates to an organic electroluminescence display panel, a fabricating method thereof, and a corresponding display device. The organic electroluminescence display panel includes: a base substrate including a display area; a gate driving circuit and a plurality of pixel driving circuits located in the display area; and a plurality of top emission type of light-emitting units located in the display area. An orthographic projection of the gate driving circuit on the base substrate at least partially overlaps with an orthographic projection of the plurality of top emission type of light-emitting units on the base substrate.

Provided are a display substrate and a detection method therefor, and a display apparatus. Compensation sub-circuits that are in one-to-one correspondence with each stage of a shift register are arranged in a gate driving circuit, and a first capacitor in each compensation sub-circuit is thus charged under the control of a detection input circuit when each stage of the shift register outputs a signal stage by stage; and an output control circuit is used to disconnect the compensation sub-circuit from a pull-up node of the corresponding stage of the shift register. The triggering of each stage of the shift register is stopped after each stage of the shift register (CR(n)) completes outputting, and the output control circuit provides a signal of a first power voltage end to the pull-up node of the corresponding stage of the shift register under the control of a second control end and the first capacitor.