One or more embodiments of the present disclosure provides a display device. The display device includes a display panel which includes a plurality of pixels; a threshold voltage sensing circuit which senses a threshold voltage of a light emitting diode included in the plurality of pixels, a data compensating circuit which corrects a data signal in accordance with a variation of the threshold voltage and accumulated data to generate a corrected data signal, and a data driver which generates a data voltage in accordance with the corrected data signal to output the data voltage to the display panel, in which the data compensating circuit periodically corrects the data signal in accordance with a look-up table in which a relationship of the variation of the threshold voltage and the accumulated data is described during an aging period to generate the corrected data signal. The display device according to the present disclosure improves an image quality of the display.

A display panel includes an array of pixels extending in a plane and arranged in rows, wherein a first plurality of the rows extend to an edge of the pixel array and one or more rows at a corner of the pixel array are recessed from the edge. The display panel includes driver circuits each connected to a corresponding row of the pixel array and occupying an area in the plane, the area having a long dimension and an orthogonal short dimension. A first set of driver circuits are connected to corresponding rows of the first plurality of rows and a second set of driver circuits are connected to corresponding rows at the corner of the pixel array. The long dimension of each of the drivers of the first set of drivers is greater than the long dimension of each of the drivers of the second set of drivers.

A display device includes: a data driver for supplying a data signal to each of a plurality of data lines; and a pixel unit including a plurality of sub-pixels. The pixel unit further includes one dummy data line disposed separate from a data line of a first column among the data lines. The data line of the first column is connected to sub-pixels disposed on odd-numbered pixel rows among sub-pixels disposed on a first pixel column, and is connected to sub-pixels disposed on even-numbered pixel rows among sub-pixels disposed on a third pixel column. The dummy data line is connected to sub-pixels disposed on the even-numbered pixel rows among the sub-pixels disposed on the first pixel column.

The present disclosure provides a display panel and a display device. The display panel includes: a base substrate, a display region including a first region, a second region and a transition region; first light-emitting elements at the first region; second light-emitting elements, first pixel circuitries and second pixel circuitries at the transition region, each first pixel circuitry being arranged between adjacent second pixel circuitries, an orthogonal projection of at least one second pixel circuitry onto the base substrate at least partially overlapping an orthogonal projection of at least one second light-emitting element onto the base substrate; first conductive lines each coupled between at least one first pixel circuitry and at least one first light-emitting element; and second conductive lines each coupled to at least one first pixel circuitry and extending along the at least one first pixel circuitry to a side away from the at least one first light-emitting element.

A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

A channel control unit and a display device using the same are provided. The channel control unit can include a data driver that converts pixel data into data voltages and supplies the data voltages to data lines, and an ineffective channel controller that receives channel data, generates dummy data during an ineffective channel section indicated by the channel data, and sends the dummy data to the data driver.

A driving chip includes a data channel block including a plurality of data channels, a scan channel block disposed in a first direction from the data channel block and including a plurality of scan channels, a data pad block disposed outside the data channel block and the scan channel block in the first direction and including a plurality of data pads which respectively receive a data signal from the plurality of data channels, and a scan pad block disposed outside the data channel block and the scan channel block in the first direction, disposed outside the data pad block in a second direction crossing the first direction and including a plurality of scan pads which respectively receive a scan signal from the scan channels.

An embodiment of the disclosure provides a circuit substrate and a tiled electronic device. The circuit substrate includes a substrate and first to third metal layers. The first metal layer is disposed on the substrate and includes first and second connection lines, and first and second scan lines. The first and second connection lines are electrically connected to the first and second scan lines, respectively. The second scan line includes two separate line segments respectively located at opposite sides of the first connection line. The second metal layer is disposed on the substrate and includes a first data line. The first data line is overlapped with the first connection line. The third metal layer is disposed on the substrate and includes a bridge line. The bridge line is electrically connected to the line segments. The second metal layer is disposed between the first and third metal layers.

Provided is a display driving circuit including a plurality of source channels configured to provide data voltages to a plurality of data lines of a display panel, respectively; a dummy channel on one side of at least one of the source channels; and control logic configured to control operations of the source channels and the dummy channel, wherein, when failure of a first source channel from among the source channels is determined, the control logic is further configured to provide data voltages to data lines corresponding to the first source channel and second source channels, respectively, which are between the first source channel and the dummy channel, by using the second source channels and the dummy channel.

In a liquid crystal device, a first pixel area is provided in a pixel area of a first substrate, and a second pixel area is provided between the first pixel area and a seal material. The first pixel area has a first pixel electrode to which an image signal is applied, the image signal having a potential alternately switching between a positive polarity and a negative polarity with reference to a first central potential. The second pixel area includes a second pixel electrode to which a first driving potential is applied, the first driving potential having a potential alternately switching between a positive polarity and a negative polarity with reference to a second central potential, the first central potential and the second central potential having a potential difference set therebetween. Therefore, ionic impurities can be efficiently swept from the first pixel area to the second pixel area.