A display device includes a pixel connected to a first gate line, an emission control line, a bias gate line, and a data line. A gate driver is configured to supply a first gate signal to the first gate line in an address scan period and configured to supply a bias write gate signal to the bias gate line in a self-scan period. An emission driver is configured to supply an emission control signal in the address scan period and in a self-scan period. A data driver is configured to supply a first data voltage to the data line in the address scan period and configured to supply a second data voltage to the data line in the self-scan period. The second data voltage is set based on the first data voltage.

A display device may include: a display panel with subpixels connected respectively to scan lines, sensing lines, and data lines; a gate driver configured to supply a scan signal to the scan lines during an active period and to supply a sensing signal to the sensing lines during a sensing period of a blank period; a data driver configured to supply a data voltage to the data lines; and a timing controller configured to control the gate and data drivers. The timing controller may determine the active period, blank period, and sensing period to be, respectively: a first active period, a first blank period, and a first sensing period for operating at the first frame rate; and a second active period, a second blank period, and a second sensing period for operating at the second frame rate. The first sensing period and the second sensing period have a same length.

Provided are a display panel and a display apparatus. In an embodiment, the display panel includes first sub-pixel rows, first gate lines, second sub-pixel rows, and second gate lines. The first sub-pixel row includes sub-pixels arranged along a first direction and is electrically connected to the first gate line. The second sub-pixel row includes sub-pixels arranged along the first direction and is electrically connected to the second sub-pixel row. The second gate line extends along the first direction. A length of the second gate line is smaller than a length of the first gate line. The display panel further includes a gate compensation line electrically connected to the second gate line. The gate compensation line and the second gate line are arranged along the second direction. The gate compensation line and the second gate line are electrically connected to a same second sub-pixel row.

A pixel circuit includes: a driving circuit configured to transmit a first initial signal received at a first initial signal terminal to a control node in response to a first reset signal received at a first reset signal terminal, write a data signal received at a data signal terminal in response to a scan signal received at a scan signal terminal, generate a driving signal according to a first voltage of a first voltage terminal and the data signal in response to an enable signal received at an enable signal terminal, and output the driving signal to an element to be driven; and a control circuit configured to transmit a control signal received at a control signal terminal to the control node in response to a voltage of the control node, so as to control a turned-on duration of the element to be driven in conjunction with the driving signal.

An array checker (AC) is described. The array checker may include software configured to implement a method. By implementing the method, the array checker may detect a location of a defect and then compensate for a shift in the defect. In particular, the method may include generating one or more reference lines in a panel. The reference lines may include a location which is known prior to generating an image of the panel. The array checker may then capture an image of the panel. The image may be captured by voltage imaging. The image may include the defect and the one or more reference lines. The method may then include calculating an offset of the reference line from the known location. The offset may then be applied to the defect location for compensating the shift in the defect.

A display device includes a pixel circuit, a drive circuit that drives a data line connected to the pixel circuit, and a capacitor that is provided between an output node of the drive circuit and the data line. The drive circuit outputs a constant current to the output node during a driving period of which a length is set according to display data.

An organic light emitting diode display device can include a driving transistor, a first transistor connected to the driving transistor, a second transistor connected between a data voltage and the driving transistor, a third transistor connected between a high level voltage and the driving transistor, a fourth transistor connected to the driving transistor, a fifth transistor connected between an initial voltage and the driving transistor, a sixth transistor connected to the initial voltage, a seventh transistor connected to the high level voltage, an eighth transistor connected to a reference voltage, a storage capacitor connected between the driving transistor and the eighth transistor, and a light emitting diode connected between a low level voltage and the fourth transistor.

A thin film transistor “TFT”) substrate includes a substrate, an active layer over the substrate, and first and second TFTs over the substrate. The active layer includes: a first drain region, a first channel region and a first source region, which function as a drain, a channel and a source of the first TFT: a first lightly doped region between the first drain region and the first channel region: a second lightly doped region between the first channel region and the first source region: and a second drain region, a second channel region and a second source region, which function as a drain, a channel and a source of the second TFT. An impurity concentration at the second drain or source region is lower than an impurity concentration at the first drain or source region and higher than an impurity concentration at the first or second channel region.

A display apparatus includes a display panel including a gate line and a data line, a controller generating a source output enable signal determining an output timing of a data voltage output to the data line, and a data driver including a signal changer, generating a final source output enable signal by using the source output enable signal, and randomly changing the output timing of the data voltage for each gate line by using the final source output enable signal.

A display device includes a pixel including a first sub-pixel emitting light of a first color and a second sub-pixel emitting light of a second color. Each of the first sub-pixel and the second sub-pixel includes: a pixel circuit layer disposed on a substrate, the pixel circuit layer including a pixel circuit, and a display element layer disposed on the pixel circuit layer, the display element layer including a light emitting element which includes an anode electrode and a cathode electrode. The pixel circuit layer includes a first contact part disposed between the substrate and the display element layer, the anode electrode and the pixel circuit being connected to each other through the first contact part to supply an anode signal to the light emitting element. A plurality of first contact parts which include a first contact part in the first sub-pixel and a first contact part in the second sub-pixel are arranged along a first direction.