A display device includes a backlight module, a liquid crystal layer, a lower polarizer, an upper polarizer, and a retardation layer. The liquid crystal layer is disposed on a lighting side of the backlight module while the lower polarizer is disposed between the liquid crystal layer and the backlight module. The upper polarizer is disposed on a side of the liquid crystal layer opposite to the lower polarizer, and the retardation layer is between the upper and lower polarizers. The retardation layer has a retardation area that may modulates the light passing through the lower polarizer and make the light passes through the upper polarizer.

The plurality of stages of circuit blocks of a driver circuit in a display device include a first transistor and a second transistor. The first transistor is connected at its gate with a first node and controls conductivity between a scanning signal line and a first clock signal line applied with a first clock signal. The first node is at an active potential when at least any one signal of signals output from one stage in each of a forward direction and a reverse direction is at the active potential. The second transistor is connected at its gate with the first node and controls conductivity between the first clock signal line and an input signal line of another stage of circuit block.

The multi-layer display system may include a plurality of display panels arranged in an overlapping manner, a backlight configured to provide light to the plurality of display panels, and a processing system. Each of the display panels may include an array of pixels. One or more of the display panels may be provided with a black mask and one or more of the display panels may be provided without a black mask to increase the transmissivity of the multi-layer display. The processing system may be configured to control the display of different content on the plurality of display panels.

A multi-layer display system may include a plurality of display panels arranged in an overlapping manner, a backlight configured to provide light to the plurality of display panels, and a processing system. Each of the display panels includes an array of pixels, each pixel including active red (R), active green (G), and active blue (B) sub-pixels. The pixels in one or more display panels may further include passive white (W) sub-pixels. The multi-layer display may further comprise a pair of crossed polarized layers. The processing system may be configured to control simultaneous display of different content on the plurality of display panels.

The present invention provides a data driver of a liquid crystal display (LCD), which comprises: a digital-to-analog converter module; the digital-to-analog converter module receives data from a clock controller of LCD, and converts to generate pixel grayscale reference voltages; the digital-to-analog converter module receives first and second gamma voltages from a gamma circuit of the LCD, and generates the pixel grayscale voltages supplied to data lines of LCD in accordance with the pixel grayscale reference voltages and the first and second gamma voltages, and wherein the first and second gamma voltages can be regulated respectively. The present invention further provides a LCD, pixel grayscale voltages supplied to four-domain sub-pixels and eight-domain sub-pixels can be regulated respectively by arranging two gamma voltages which can be regulated respectively, so as to resolve the problem of color shift occurred when the LCD displays.

In a liquid crystal display device (100), each pixel row group is selected by a common scan signal voltage, each pixel row group including N pixel rows which adjoin one another in a column direction. Where two pixel rows which adjoin each other in a column direction and which are included in different pixel row groups are a first pixel row and a second pixel row, the first pixel row includes a pixel which has a pixel electrode (16) capacitively coupled with a gate bus line (12) which is associated with the second pixel row. When the first pixel row is included in the q.sup.th group, the second pixel row is included in the (q+1).sup.th group. A scan signal voltage supplied to gate bus lines which are associated with the (q+1).sup.th group switches from low to high before a scan signal voltage supplied to gate bus lines which are associated with the q.sup.th group switches from high to low.

The plurality of stages of circuit blocks of a driver circuit in a display device include a first transistor and a second transistor. The first transistor is connected at its gate with a first node and controls conductivity between a scanning signal line and a first clock signal line applied with a first clock signal. The first node is at an active potential when at least any one signal of signals output from one stage in each of a forward direction and a reverse direction is at the active potential. The second transistor is connected at its gate with the first node and controls conductivity between the first clock signal line and an input signal line of another stage of circuit block.

A curvature-adjustable display device includes: a detection module configured to detect a curvature of the display device and send the curvature; a backlight module including a plurality of backlight substructures, in which each backlight substructure is configured to provide backlight for different areas of the display device according to a backlight driving parameter matched with the backlight substructure; a driver module which is configured to receive the curvature sent by the detection module, determine the backlight driving parameter required by each backlight substructure according to the received curvature and a preset corresponding relationship between the curvature and the backlight driving parameter, and send the backlight driving parameter to each corresponding backlight substructure, respectively, so that the backlight substructures can provide backlight for different areas of the display device according to the backlight driving parameter matched with the backlight substructure; and a display panel configured to display images.

The present invention provides a test circuit of gate driver on array (GOA) and a test method of GOA. The test circuit of GOA comprises a first wiring arranged outside the area where the plurality of display panels is located; a second wiring located between two of the adjacent regions; a switch unit arranged between the first wiring and the second wiring, wherein the area is divided into a plurality of areas where the display panel is located.

An array substrate and a display panel are provided. The array substrate includes a first substrate, a plurality of scanning lines and a plurality of data lines disposed on a first side of the first substrate and being intersected to define a plurality of sub-pixels including first, second, third, and fourth sub-pixels arranged alternatingly and repeatedly along a row direction, and a plurality of support structures disposed on the first side of the first substrate. Along a column direction, the plurality of sub-pixels are divided into first sub-pixel columns containing the first and third sub-pixels arranged alternatingly, and second sub-pixel columns containing the second and fourth sub-pixels arranged alternatingly. A projection of a region where the fourth sub-pixel is located on the first substrate covers a projection of a support structure on the first substrate, and the row direction is different from the column direction.