A gate signal line driving circuit which suppresses noises in a gate signal and a display device which uses the gate signal line driving circuit are provided. A first basic circuit provided to a gate signal line driving circuit includes a HIGH voltage applying switching element which applies a HIGH voltage to gate signal lines in response to a signal HIGH period, and a LOW voltage applying switching circuit which applies a LOW voltage to the gate signal lines in response to a signal LOW period. In response to a signal HIGH period, a switch of the LOW voltage applying switching circuit of the first basic circuit is turned off based on a signal applied to a switch of the HIGH voltage applying switching element of a second basic circuit which assumes a signal HIGH period earlier than the first basic circuit.

A liquid crystal display device wherein a first substrate and a second substrate are bonded together by a sealing material, a pixel electrode, a common electrode, a shift register, a clock line, and a power supply line are formed on the first substrate, a plurality of conductive particles are mixed into the sealing material, the plurality of conductive particles are maintained at a same potential as the common electrode, and the plurality of conductive particles are disposed at a position overlapping at least a part of the power supply line, when viewed from a normal direction of the first substrate.

A low-resolution image is displayed at higher resolution and afterimages are reduced. Resolution is made higher by super-resolution processing. In this case, the super-resolution processing is performed after frame interpolation processing is performed. Further, in that case, the super-resolution processing is performed using a plurality of processing systems. Therefore, even when frame frequency is made higher, the super-resolution processing can be performed at high speed. Further, since frame rate doubling is performed by the frame interpolation processing, afterimages can be reduced.

The invention discloses a GOA circuit, a display device and a drive method of a GOA circuit, the GOA circuit is set to be GOA units including a plurality of levels, a N leveled GOA unit is applied to charge a N leveled scanning line of a display region of the display device, the N leveled scanning line is connected to a first gate all on signal and a second gate all on signal, which can guarantee scanning lines corresponding to all the GOA units are being charged under control of the first gate all on signal and the second gate all on signal. The invention can carry out an all gate on function according to the method above.

A method of driving a display panel, the method including generating a data signal including a black voltage signal and a white voltage signal, measuring brightness levels of pixels, converting differences between the measured brightness levels into direct current (DC) voltages, resetting the black voltage signal to reduce a difference between the DC voltages, generating a data voltage based on the data signal to output the data voltage to the display panel, and displaying an image on the display panel based on the data voltage.

The present invention relates to a liquid crystal display (LCD) device which is capable of improving picture quality by switching an optimal gamma voltage and an optimal common voltage on a basis of an operation time, and a method for driving the same. The liquid crystal display device includes a timing controller, a voltage generating unit, a data driver, and a liquid crystal panel. The timing controller can generate voltage control signal for switching initial state to stable state by using certain switching point. The voltage generating unit can receive the voltage control signal, supply the first gamma voltage and the first common voltage during the initial state, and supply the second gamma voltage and the second common voltage during the stable state. The data driver can receive the first gamma voltage in the initial state and the second gamma voltage in the stable state. The liquid crystal panel can suppress short-term residual image if the first gamma voltage and the first common voltage are supplied, and can suppress long-term residual image if the second gamma voltage and the second common voltage are supplied.

An array substrate and a display panel are provided. The array substrate includes a first substrate, a plurality of scanning lines and a plurality of data lines disposed on a first side of the first substrate and being intersected to define a plurality of sub-pixels including first, second, third, and fourth sub-pixels arranged alternatingly and repeatedly along a row direction, and a plurality of support structures disposed on the first side of the first substrate. Along a column direction, the plurality of sub-pixels are divided into first sub-pixel columns containing the first and third sub-pixels arranged alternatingly, and second sub-pixel columns containing the second and fourth sub-pixels arranged alternatingly. A projection of a region where the fourth sub-pixel is located on the first substrate covers a projection of a support structure on the first substrate, and the row direction is different from the column direction.

A display device includes a first signal electrode configured to transfer a signal, a first insulating layer positioned on the first signal electrode, a first electrode positioned on the first insulating layer, a second insulating layer positioned on the first electrode, and a second electrode positioned on the second insulating layer, where a first contact hole exposing the first signal electrode is defined in the first insulating layer and the second insulating layer, the second electrode is connected with the first signal electrode through the first contact hole, and an opening including an edge side surrounding the first contact hole in a plan view is defined in the first electrode.

An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line.

Provided is a liquid crystal display device, including a first and second substrates, the second substrate including data signal lines, gate signal lines, pixel electrodes, a plurality of common electrodes that extend in one of a column direction and a row direction, and a plurality of shield electrodes overlapping at least one of the data signal lines or the gate signal lines, the plurality of common electrodes including a first common electrode to which a first voltage is supplied and a second common electrode to which a second voltage is supplied, the first common electrode and the second common electrode being alternately arranged in one of the row direction and the column direction, in which, in plan view, each of the plurality of shield electrodes is formed to overlap at least a gap formed between the first common electrode and the second common electrode that are adjacent to each other.