A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, and the driving module includes a driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, and the non-light-emitting stage includes a bias adjustment stage, in which one of a source and a drain of the driving transistor receives a bias adjustment signal. An operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2, where L1>L2. A working process of the display panel in the first mode includes a first frame, and a working process of the display panel in the second mode includes a second frame.

A display backplane is provided, including a base, wherein pixel circuits, bonding electrodes, and bonding connection wires are on the base; the bonding electrodes are coupled to the bonding connection wires in a one-to-one correspondence; the bonding electrodes and the bonding connection wires are on two opposite surfaces of the base; the pixel circuits and the bonding connection wires are on a same side of the base; one end of each bonding connection wire is coupled to the bonding electrode through the first via in the base; the other end of each of at least some bonding connection wires is coupled to the pixel circuit; and an orthographic projection of at least one of the bonding electrodes and the bonding connection wires on the base is not coincident with an orthographic projection of the pixel circuit on the base.

A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations.

In a display panel, pixels each including a plurality of sub-pixels are arranged in a matrix form, wherein each of the plurality of sub-pixels includes: an inorganic light-emitting element; a constant current generator circuit that provides a driving current to the inorganic light-emitting element on the basis of a constant current generator data voltage; and a PWM circuit for controlling the time for the driving current to flow through the inorganic light-emitting element on the basis of a PWM data voltage, wherein the constant current generator circuit includes a first driving transistor and the PWM circuit includes a second driving transistor, and wherein the constant current generator circuit or the PWM circuit comprises an internal compensation circuit that compensates for electrical characteristics of the first driving transistor and the second driving transistor.

The present disclosure provides a display device and a driving circuit. In the display device, a first subpixel is connected to a first data line and a first reference voltage line, and includes an emitting device and a driving transistor; and a second subpixel is connected to a second data line and a second reference voltage line, and includes an emitting device and a driving transistor. The driving time of the first subpixel includes a first initialization time in which a reference voltage is applied to the first reference voltage line and a first tracking time in which a voltage of the first reference voltage line increases from the reference voltage and then is saturated. Sensing times for subpixels having different channel sizes are reduced.

A pixel driving circuit includes a reset sub-circuit, a compensation sub-circuit, a light-emitting control sub-circuit and a driving sub-circuit. The reset sub-circuit is configured to transmit an initialization signal received from an initialization signal terminal to the light-emitting control sub-circuit. The fight-emitting control sub-circuit is configured to transmit the initialization signal to the first node. The compensation sub-circuit is configured to transmit the initialization signal from the first node to a second node so as to reset a voltage of the second node. The driving sub-circuit is configured to open a conductive path from a first voltage signal terminal to the initialization signal terminal during a process of resetting the voltage of the second node.

A display device may include a display panel and a driver circuit. The display panel may include subpixels, data lines, and reference voltage lines. The driver circuit may drive the data lines. A first subpixel may be connected to a first data line and a first reference voltage line. A driving time of the first subpixel may include a first initialization time in which a reference voltage is applied to the first reference voltage line and a first tracking time in which a voltage of the first reference voltage line increases from the reference voltage. During the first tracking time, a first data signal transferred to the first subpixel through the first data line may be changed from a first voltage value to a reference driving voltage value. The first voltage value may be higher than the reference driving voltage value. The display device may reduce a sensing time.

A display device includes a display panel on which a plurality of sub-pixels are disposed; a timing controller configured to transmit an image control signal to a host system to receive image data from the host system; a data driving circuit configured to convert the image data transmitted from the timing controller into a data voltage and configured to supply the data voltage to the display panel; and a semi-off switching circuit configured to control the image control signal so that the image data is cut off from the host system during a semi-off period of a predetermined time from a time when an off monitoring signal is transmitted from the host system in response to the power off signal.

Provided are a display panel and a display device. The display panel includes a pixel driver circuit. The pixel driver circuit includes a light-emitting module, a drive transistor and at least one light-emitting control transistor. The drive transistor, the light-emitting control transistor and the light-emitting module are connected in series between a first power supply signal terminal and a second power supply signal terminal, and at least one of the drive transistor or the light-emitting control transistor is a first double-gate transistor. The first double-gate transistor includes a first gate, a second gate and a first source, and the second gate is electrically connected to the first source.

A display device includes pixels including a first pixel and a second pixel sequentially disposed in a first direction, each including sub-pixels including a first electrode, a second electrode, and a light emitting element, a driving circuit including driving elements between the pixels, pixel lines connected to the pixels, and driving lines connected to the driving elements. The driving lines are in an area between the first pixel and the second pixel, and include a first driving line extending in a second direction intersecting the first direction in the area between the first pixel and the second pixel. First electrodes included in the sub-pixels of the first pixel and first electrodes included in the sub-pixels of the second pixel are spaced apart by a distance equal to or greater than a width of the first driving line in the first direction, and do not overlap the first driving line.