A display device includes: pixel electrodes including a first pixel electrode and a second pixel electrode adjacent to the first pixel electrode in a first direction; switching elements including a first switching element coupled to the first pixel electrode and a second switching element coupled to the second pixel electrode; gate lines including a first gate line coupled to the first switching element and a second gate line coupled to the second switching element; a gate driver supplying a gate signal to the gate lines; and drive electrodes including a first drive electrode and a second drive electrode adjacent to the first drive electrode in the first direction. The first drive electrode overlaps the first and second pixel electrodes, and the second gate line. The second drive electrode overlaps the first gate line. The gate driver supplies the gate signal to the first and second gate lines simultaneously.

A scan driver circuit including shift register units and gate control circuits is provided. The shift register units are in a peripheral area of a display panel, and for receiving first clock signals. The gate control circuits are in an active area of the display panel, and for receiving second clock signals. Each shift register unit is coupled with corresponding N of the gate control circuits, and for providing a corresponding one of the first clock signals as a control signal to the corresponding N of the gate control circuits. The corresponding N of the gate control circuits are coupled with corresponding M of gate lines. The corresponding N of the gate control circuits are for providing, according to the control signal, corresponding M of the second clock signals as M gate signals to the corresponding M of gate lines, in which M and N are positive integers.

Embodiments of the present disclosure provide a method of driving display, and a display device. The method of driving display includes: scanning, progressively or rows by rows, a plurality of sub-pixels arranged in an N×M array, to turn on each row of sub-pixels scanned, so that a duration in which two adjacent rows of sub-pixels are simultaneously in an ON state is greater than or equal to two times a unit scanning time, wherein the unit scanning time is a time required for scanning a row of sub-pixels, N is an integer greater than 1, and M is an integer greater than 1; and applying data signals to at least two rows of sub-pixels simultaneously in the ON state, so that a duration of applying the data signals to each row of sub-pixels is greater than the unit scanning time.

To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor, a clock signal is input to a gate electrode of the first switching transistor, and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

A gate driver includes at least one stage, which includes: a first output circuit configured to supply a voltage of a first power source or a voltage of a second power source to a first output terminal and including a fourth capacitor connected between a second node and the first output terminal; a second output circuit configured to supply a signal supplied to a fourth input terminal or the voltage of the second power source to a second output terminal; an input circuit configured to control a voltage of the second node and a voltage of a third node; a first signal processor configured to control a voltage of a first node; a second signal processor configured to control the voltage of the second node; and a third signal processor connected between the first node and the third node, and configured to control the voltage of the first node.

In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

Embodiments of the present disclosure relate to a data driving circuit, a controller and a display device. A display driving is performed by outputting the number of internal data enable signals that is smaller than the number of external data enable signals in the display device performing high-speed driving. As a result, it is possible to prevent an increase in the load of the data driving circuit according to the high-speed driving. In addition, a part of the internal data enable signals is output during a blank period to prevent a decrease in the interval between the internal data enable signals and to increase the number of internal data enable signals. This can improve the image quality displayed on the display panel while preventing an increase in the load on the data driving circuit.

A display device, includes: a scan driver configured to sequentially supply scan signals having a turn-on level to the first scan line and the second scan line during a first period and to concurrently supply scan signals having a turn-on level to the first scan line and the second scan line during a second period after the first period, wherein: a mask period corresponds to a difference between a start point of the second period and a start point of the first period in a next frame period, a first frame period and a second frame period have different mask periods, a third frame period between the first frame period and the second frame period has a same mask period as the first frame period, and a fourth frame period between the first frame period and the second frame period has a same mask period as the second frame period.

A display panel, an electronic device and a method are provided. The display panel includes: a base substrate; a plurality of sub-pixels arranged in a matrix; a plurality of data lines and a plurality of gate lines, the data line intersect the gate line; at least some of the plurality of sub-pixels are divided into a plurality of sub-pixel association groups, each sub-pixel association group includes a plurality of sub-pixels of a same color electrically connected to a same data line; the display panel further includes an associated pixel control circuit configured to independently perform data writing on the plurality of sub-pixels of the same color in the sub-pixel association group in the first image display mode; and synchronously perform data writing on the plurality of sub-pixels of the same color electrically connected to the same data line in the sub-pixel association group in the second image display mode.