A display panel is provided and has a first display region including a plurality of first light-emitting elements, a third display region including a plurality of third light-emitting elements and a plurality of third pixel circuits, and a second display region therebetween, the second display region comprises a plurality of second light-emitting elements, a plurality of first pixel circuits and a plurality of second pixel circuits, each first pixel circuit is connected to at least one first light-emitting element through a conductive wire, and each second pixel circuits is connected to at least one second light-emitting element; each third light-emitting element is connected to at least one third light-emitting element; the first display region, the second display region and the third display region increase sequentially in area, and the first pixel circuit and the second pixel circuit are both less than the third pixel circuit in area.

In a display device having a non-rectangular display unit, occurrence of a difference in luminance between a region with a high load and a region with a low load is suppressed. A region inside the display unit is segmented into a high-load region with a high load on horizontal scanning lines (an initialization control line and a write control line) and a low-load region with a low load on horizontal scanning lines. An initialization control line and a write control line that are disposed in the high-load region are driven by a discharge driver and a scan driver, respectively. An initialization control line and a write control line that are disposed in the low-load region both are driven by, for example, the discharge driver.

A display device includes light emitting elements arranged in a matrix and pixel circuits arranged in a matrix. A pixel circuit includes a first reset sub-circuit, a node control sub-circuit, a light emitting control sub-circuit and a second reset sub-circuit. The first reset sub-circuit is configured to provide a signal of an initial signal line to a first node. The node control sub-circuit is configured to provide a signal of a data signal line to a second node, and compensate the first node until a voltage of the first node meets a threshold condition. The light emitting control sub-circuit is configured to provide a signal of a first power supply line to the second node and provide a signal of a third node to a light emitting element. The second reset sub-circuit is configured to provide a signal of the initial signal line to the light emitting element.

A driving transistor is configured to control driving current for the light-emitting element. A first capacitive element and a second capacitive element are connected in series between a gate and a source of the driving transistor. A first switching transistor is configured to switch connection/disconnection between a data line and an intermediate node located between the first capacitive element and the second capacitive element. A second switching transistor is configured to switch connection/disconnection between the gate and a drain of the driving transistor. A third switching transistor is configured to switch connection/disconnection between the intermediate node and a reference power line. A fourth switching transistor is configured to switch supply/non-supply of driving current from the driving transistor to the light-emitting element. A fifth switching transistor is configured to switch connection/disconnection between an anode of the light-emitting element and a reset power line.

A display device includes: a display panel including pixels, a data driving circuit, a scan driving circuit which drives a plurality of first scan lines and a plurality of second scan lines, and a driving controller which controls the data driving circuit and the scan driving circuit to drive a first display area of the display panel at a first operating frequency and drive a second display area of the display panel at a second operating frequency lower than the first operating frequency while an operating mode is a multi-frequency mode. During the multi-frequency mode, first scan signals provided to first scan lines, which correspond to the second display area, of the plurality of first scan lines are maintained at inactive levels in predetermined frames, and second scan signals provided to the plurality of second scan lines transition to active levels at least twice in each of the predetermined frames.

A display device includes a substrate including a display area and a peripheral area disposed around the display area. The peripheral area includes a bending region and a contact region adjacent to the bending region. A first connection line includes a first portion disposed in the contact region, and a second portion disposed in both the bending region and the contact region, and including a first layer and a second layer. At least part of the second layer of the second portion overlaps the first layer of the second portion. In the contact region, the first layer of the second portion is electrically connected to the first portion, and the second layer of the second portion is electrically connected to the first layer of the second portion.

Disclosed are an array substrate and a manufacturing method thereof, a display panel, a display device and a pixel driving circuit. The array substrate includes: a base substrate; and a wiring layer and an effective light-emitting layer formed and stacked on the base substrate sequentially, wherein the wiring layer includes a first wiring and a second wiring, an orthographic projection of the first wiring on the base substrate overlaps an orthographic projection of the effective light-emitting layer on the base substrate to form a first overlapping area, an orthographic projection of the second wring on the base substrate overlaps the orthographic projection of the effective light-emitting layer on the base substrate to form a second overlapping area, and the first overlapping area and the second overlapping area are respectively located on both sides of a central line of the orthographic projection of the effective light-emitting layer on the base substrate.

A display panel includes a plurality of pixels arranged in a matrix, the plurality of pixels respectively including a plurality of sub pixels. The plurality of sub pixels respectively includes a light emitting element, and a PWM pixel circuit configured to control a light emitting duration of the light emitting element, based on a pulse width modulation (PWM) data voltage and a sweep voltage. A plurality of PWM pixel circuits included in the display panel are driven, for each of row lines of the plurality of pixels, in an order of a data setting period for setting the PWM data voltage and then a light emitting period in which the light emitting element emits light during a duration corresponding to the set PWM data voltage according to a change of the sweep voltage.

A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

A display apparatus according to the present disclosure includes: a pixel array unit, pixels being arranged in the pixel unit, the pixels each including a driving transistor that includes a plurality of gate electrodes and drives a light emitting unit in response to a video signal applied to one gate electrode of the plurality of gate electrodes; and a control unit that controls gate voltage of a different gate electrode of the driving transistor. Further, an electronic apparatus according to the present disclosure includes the display apparatus having the above-mentioned configuration.