A display apparatus includes a display panel, a gamma reference voltage generator and a data driver. The gamma reference voltage generator is configured to generate a gamma reference voltage. The gamma reference voltage includes a gamma amplifier configured to output the gamma reference voltage. The data driver is configured to generate a data voltage based on the gamma reference voltage and to output the data voltage to the display panel. A polarity of an offset voltage of the gamma amplifier is inverted alternately in a unit of one frame and in a unit of two frames.

A display device includes a substrate, a pixel array placed on a first surface side of the substrate, light emission control signal lines, scanning signal lines, a scanning signal line driving circuit, and a driving control signal line. The driving control signal line includes a first portion, a second portion, and third portions. The light emission control signal lines include a first light emission control signal line and a second light emission control signal line, and a number of intersecting portions of the first light emission control signal line and the first portion is smaller than a number of intersecting portions of the second light emission control signal line and the third portions.

One embodiment describes an electronic display that displays image frames with a first refresh rate or a second refresh rate, in which the second refresh rate is lower than the first refresh rate; a display driver that writes the image frames by applying voltage to a display panel; and a timing controller that receives first image data from an image source, in which the first image data describes a first image frame and a first desired refresh rate equal to the second fresh rate; and that instructs the display driver to apply a first set of voltage polarities to the display panel to display first image frame at the first refresh rate and to apply a second set of voltage polarities to the display the first image frame at the second refresh rate when polarity of inversion imbalance accumulated is equal to polarity of the first set of voltage polarities.

A display unit includes: a display section having an electrophoretic display device provided among a plurality of first electrodes and a second electrode, and displaying an image by switching a white, black, or gray-scale display state depending on an applied voltage; and a drive circuit driving the display section by varying a voltage applied to the first electrodes, while holding the second electrode at a common potential during a write period including frame period(s). When a first region of the display section has a first display state of white or black during a first write period, and an image of a second region thereof is changed while holding the first display state at the first region upon switchover from the first write period to a temporally-continued second write period, the drive circuit offsets the common potential toward a direction in which a voltage applied to the first region is raised.

To suppress a malfunction of a circuit due to deterioration in a transistor. In a transistor which continuously outputs signals having certain levels (e.g., L-level signals) in a pixel or a circuit, the direction of current flowing through the transistor is changed (inverted). That is, by changing the level of voltage applied to a first terminal and a second terminal (terminals serving as a source and a drain) every given period, the source and the drain are switched every given period. Specifically, in a portion which successively outputs signals having certain levels (e.g., L-level signals) in a circuit including a transistor, L-level signals having a plurality of different potentials (L-level signals whose potentials are changed every given period) are used as the signals having certain levels.

The present application provides a method for controlling an offset voltage in a display device, a display device and a storage medium. The method for controlling an offset voltage in a display device comprises: generating a chopper signal based on at least one of a data output control signal and a polarity inversion control signal; and, controlling, according the chopper signal, the polarity of an offset voltage of an operational amplifier in the display device, so that the offset voltage is equivalently eliminated within at least one of a design space range and a design time range. By using the control method of the present application, without using large-size transistors and providing more signals, the display effect can be ensured and the size of the chip can also be reduced.

The present disclosure relates to a power supply device including a gate driving circuit configured to supply gate signals to a plurality of gate lines, a first power supply circuit configured to supply a first initialization voltage having a voltage level between a first voltage level and a second voltage level to a plurality of first initialization power lines, the first initialization voltage having the first voltage level in a first period, a third voltage level between the first and second voltage levels in a second period, and the second voltage level in a third period, and a second power supply circuit configured to supply a driving voltage to a plurality of driving power lines among the plurality of power lines, and a display device including the power supply device.

A display device includes: a common electrode and a pixel electrode that includes a horizontal stem, a vertical stem, and a branch. A pixel of the branch includes a first branch that extends in a first diagonal direction from the horizontal stem and the vertical stem, and a second branch that extends in a second diagonal direction from the horizontal stem and the vertical stem.

To suppress a malfunction of a circuit due to deterioration in a transistor. In a transistor which continuously outputs signals having certain levels (e.g., L-level signals) in a pixel or a circuit, the direction of current flowing through the transistor is changed (inverted). That is, by changing the level of voltage applied to a first terminal and a second terminal (terminals serving as a source and a drain) every given period, the source and the drain are switched every given period. Specifically, in a portion which successively outputs signals having certain levels (e.g., L-level signals) in a circuit

including a transistor, L-level signals having a plurality of different potentials (L-level signals whose potentials are changed every given period) are used as the signals having certain levels.

The present disclosure relates to a method of electrically aging a PMOS thin film transistor. The method includes applying a first voltage Vg with an amplitude of A volts to a gate of the PMOS thin film transistor; applying a second voltage Vs with an amplitude of (A-40) to (A-8) volts to a source of the PMOS thin film transistor; and applying a third voltage Vd with an amplitude of (A-80) to (A-16) volts to a drain of the PMOS thin film transistor. Application of the first voltage Vg, the second voltage Vs and the third voltage Vd is maintained for a predetermined time period, and Vd−Vs<0. In this way, reduction of a leakage current of the PMOS thin film transistor is achieved without changing a structural design of the thin film transistor.