A display apparatus includes a display panel having a plurality of gate lines, a plurality of data lines, and a plurality of subpixels. Each of the plurality of subpixels includes a subpixel electrode connected to one of the plurality of gate lines and one of the plurality of data lines through a switching element. A gate driver is configured to output a plurality of gate signals to the plurality of gate lines and to deactivate at least one of the plurality of gate signals in a P-th frame. A data driver is configured to output a plurality of data voltages to the plurality of data lines. Here, P is a positive integer.

A shift register unit and a driving method thereof, a gate driving circuit, and a display device are provided. In the shift register unit, the input circuit inputs an input signal to a first node; the output circuit outputs an output signal to an output terminal; the first control circuit performs a first control on a level of a first control node; the first noise reduction control circuit controls a level of a second node; the second control circuit performs a second control on a level of a second control node; the second noise reduction control circuit controls a level of a third node; the first voltage-stabilizing circuit performs a third control on the level of the second control node, and the second control and the third control cause at least part of the second noise reduction control circuit to be in different bias states.

A shift register, a gate drive circuit, and a display panel are provided. The shift register includes an input sub-circuit configured to pre-charge a pull-up node using an input signal; an output sub-circuit configured to output a clock signal through an signal output terminal; a pull-down control sub-circuit configured to control a potential of a pull-down node using a power supply voltage signal; a first pull-down sub-circuit configured to pull down a potential of the pull-down node using a first preset voltage signal; and a first control sub-circuit configured to control the potential of the pull-up node using a second preset voltage signal in response to the potential of the pull-down node; a potential of the first preset voltage signal is lower than a potential of a non-operating level signal of the first pull-down sub-circuit, but higher than a potential of the second preset voltage signal.

The present application provides a GOA circuit and a display panel. In the GOA circuit, one of two GOA units of a same stage in GOA sub circuits at left and right sides of the display panel is deployed only with an all-on module and the other one of the two GOA units is deployed only with an all-off module. In such a way, both the number of the all-on modules and the number of the all-off modules required in the GOA unit are halved, thereby reducing the area occupied by the GOA circuit. It is beneficial for realizing a display panel with a narrow bezel.

A display device is provided, the display device includes a first display portion, a second display portion not in a same plane with the first display portion, and a side display portion connected between the first display portion and the second display portion, a brightness of the second display portion is less than a brightness of the first display portion and a brightness of the side display portion.

A display device includes a first switching element including a second electrode and a first gate electrode, a second switching element including a third electrode connected with the first gate electrode, a third switching element including a fifth electrode connected with the second electrode, and sixth electrode, a fourth switching element including a seventh electrode connected with the second electrode, and an eighth electrode, a fifth switching element including a ninth electrode connected with the second electrode, and a tenth electrode, a first light emitting diode connected with the sixth electrode and the eighth electrode, a second light emitting diode connected with the eighth electrode and the sixth electrode, and a switch selectively connecting a common power source line with the sixth electrode or the eighth electrode. The first light emitting diode and the second light emitting diode have different polarities from each other with respect to a same direction.

A shift register circuit includes a denoising control sub-circuit and a denoising sub-circuit. The denoting control sub-circuit is configured to generate an alternating voltage signal according to a voltage of a first voltage terminal and a signal of a second clock signal terminal in response to a signal of a first clock signal terminal, to rectify the alternating voltage signal and then to output a signal to a first denoising control node, so that the voltage of the first denoting control node is maintained to be a voltage that enables the denoising sub-circuit to be turned on. The denoting sub-circuit is configured to denoise a scan signal output terminal in response to a voltage of the first denoising control node being the voltage that enables the denoising sub-circuit to be turned on.

A display substrate and a display panel are provided. The display substrate includes a base substrate; the base substrate includes a display region and a peripheral region on at least one side of the display region; the peripheral region includes a first peripheral sub-region and a second peripheral sub-region, the display region includes a first display sub-region corresponding to the first peripheral sub-region and a second display sub-region corresponding to the second peripheral sub-region, and the second display sub-region is different from the first display sub-region; the second peripheral sub-region includes a first gate driving circuit, and the first gate driving circuit is configured to be connected to a plurality of gate scanning signal lines in the first display sub-region through a plurality of connecting lines in the display region, to respectively providing a gate scanning signal to a plurality of rows of pixel units in the first display sub-region.

Provided are a driving method for a display panel, display driving device and electronic apparatus. The display panel includes a shift register. A drive signal of the shift register includes a trigger signal and a clock signal. The driving method includes: a current FPS in a current display mode is acquired; a current trigger signal and a current clock signal of the shift register is determined according to the current FPS; the shift register is provided with the current trigger signal and the current clock signal. A refresh frequency of the current trigger signal is the same as the current FPS. The current clock signal is the same as a reference clock signal in a reference display mode at least within an effective action duration of the current trigger signal. The current FPS is less than or equal to the reference FPS in the reference display mode.

A scan-type display apparatus includes an LED array, a display module, a control module and a driver module. The LED array has a common anode configuration. The control module generates a synchronization control (SC) signal. Based on the SC signal, the driver module outputs an input voltage to scan lines of the LED array sequentially without overlapping in time so as to drive LEDs of the LED array to emit light in a line scan manner, and generates an image refresh signal that is related to the output of the input voltage to one of the scan lines which corresponds to a last line of the line scan in each line scan cycle and that is further related to refreshing of images on a display constituted by the LED array and the display module.