A shift register comprises a first shift register unit and a second shift register unit. The first shift register unit comprises a first input circuit connected to a first input terminal and a first pull-up node, a first output circuit connected to the first pull-up node, a first output terminal and a first clock terminal, and a first pull-down circuit. The second shift register unit comprises a second input circuit connected to a second input terminal and a second pull-up node, and a second output circuit connected to the second pull-up node, a second output terminal and a second clock signal.

Provided are a display panel and display device. The display panel includes a driver circuit comprising a shift register that is N-stage cascaded; wherein the shift register comprises: a third control unit configured to receive a first voltage signal and generate an output signal in response to a signal of a third node, or receive a second voltage signal and generate an output signal in response to a signal of a second node; and a fourth control comprising a first capacitor and a first transistor, wherein a second plate of the first capacitor is connected to a drain of the first transistor, a source of the first transistor receives a first control signal, and a gate of the first transistor receives a second control signal.

Embodiments of the present disclosure provide a method of driving display, and a display device. The method of driving display includes: scanning, progressively or rows by rows, a plurality of sub-pixels arranged in an N×M array, to turn on each row of sub-pixels scanned, so that a duration in which two adjacent rows of sub-pixels are simultaneously in an ON state is greater than or equal to two times a unit scanning time, wherein the unit scanning time is a time required for scanning a row of sub-pixels, N is an integer greater than 1, and M is an integer greater than 1; and applying data signals to at least two rows of sub-pixels simultaneously in the ON state, so that a duration of applying the data signals to each row of sub-pixels is greater than the unit scanning time.

The embodiments of the application discloses a driving circuit, a display panel, a display apparatus and a voltage stabilization control method. The driving circuit includes an input module, a control module, an output module and a voltage stabilization module. The output module is used to output a scan signal via the output module according to level states of signals at first and second nodes. With respect to the voltage stabilization module, an input terminal thereof is connected to the output terminal of the output module, a first control terminal thereof receives a second clock signal, a second control terminal thereof is connected to the second node, an output terminal thereof is connected to the first node, and the voltage stabilization module is to connect the output terminal of the output module to the first node, when the scan signal is to control a data writing transistor to be turned off.

A display device includes a display panel including data lines configured to receive an image signal, gate lines configured to receive a scan signal, and gate connection lines configured to transmit the scan signal to the gate lines; and a multi-chip film package including, on a film, a first gate integrated circuit (IC) configured to transmit a first scan signal to the gate connection lines through first gate output lines, a second gate IC configured to transmit a second scan signal to the gate connection lines through second gate output lines, and a source IC configured to transmit the image signal to the data lines through source output lines. Each of the first gate output lines is between two adjacent source output lines, and each of the second gate output lines is between two adjacent source output lines.

A light emitting display apparatus includes a gate driver including stages provided in a substrate and a plurality of gate lines connected to the stages. Each of the stages includes a shift register and two buffers connected to the shift register, a first buffer of two buffers configuring an n.sup.th stage and a first shift register configuring the n.sup.th stage are provided in an n.sup.th horizontal portion and a second buffer of the two buffers is provided in an n+2.sup.th horizontal portion, a third buffer of two buffers configuring an n+1.sup.th stage and a second shift register configuring the n+1.sup.th stage are provided in an n+3.sup.th horizontal portion and a fourth buffer of the two buffers is provided in an n+1.sup.th horizontal portion, and the n.sup.th horizontal portion is a region including pixels which are arranged along a 4n−3.sup.th gate line and a 4n−2.sup.th gate line.

According to embodiments of the disclosure, a gate driving circuit and a display device may include four buffer groups for driving 4k scan lines, two common logic units for controlling the four buffer groups, and a common sensing circuit controlling to output a sensing driving scan signal to at least one scan line among the 4k scan lines. Thus, it is possible to allow the gate driving circuit to have a low-area structure and to reduce the bezel area of the display device.

A display device includes a display panel including a first pixel connected to a first initialization scan line and a first compensation scan line and a second pixel connected to a second initialization scan line and a second compensation scan line, a scan driving circuit which provides a first initialization scan signal to the first initialization scan line and the second initialization scan line in common and provides a first compensation scan signal and a second compensation scan signal to the first compensation scan line and the second compensation scan line, and a driving controller which controls the scan driving circuit. A delay time from a time point at which the first initialization scan signal transitions from an active level to an inactive level to a time point at which the first compensation scan signal transitions from the inactive level to the active level is less than one horizontal period.

A display device includes a display panel, an input sensing unit, input sensing pads, a shift register, and a multiplexer circuit. The display panel includes a display area and a non-display area. The input sensing unit is disposed on the display panel. The input sensing unit includes sensing electrodes and signal lines respectively connected to the sensing electrodes. The input sensing pads are disposed in the non-display area. The input sensing pads include control signal pads and a sensing pad. The shift register array is configured to receive a start signal and at least one clock signal through some of the control signal pads, and to sequentially activate first selection signals. The multiplexer circuit is configured to selectively connect the signal lines to the sensing pad in response to the first selection signals.

A display panel and a display device are provided. The display panel and display device include gate driver on array (GOA) units in a first column, GOA units in a second column, and signal input lines. By adjusting a positional relationship between the signal input line and the GOA units in the first column and the GOA unit in the second column, the GOA units in the first column and the GOA units in the second column may share the signal input line, so as to save a set of signal input lines and reduce a width of the frame area.