Disclosed is a display device, including: a substrate including a pixel area and a peripheral area; pixels provided in the pixel area as a plurality of pixel rows and a plurality of pixel columns; data lines configured to provide a data signal; scan lines configured to provide a scan signal; first power lines configured to provide a power source to the pixel columns; and a second power line connected to the first power lines and disposed in the peripheral area. A scan line connected to an i.sup.th pixel row may apply a scan signal to the i.sup.th pixel row, and a branched line branched from the scan line may apply an initialization signal to a k.sup.th pixel row (k≠i). A branched point of the scan line is disposed between a pixel most adjacent to the second power line of the i.sup.th pixel row and the second power line.

A display substrate and a display apparatus are disclosed. The display substrate includes a display region and a peripheral region, the peripheral region includes a circuit region, and the display region includes a plurality of sub-pixels, a plurality of data lines extending along a first direction and a plurality of gate lines extending along a second direction crossing the first direction. The circuit region includes a plurality of driving unit groups. The circuit region includes a first sub-region and a second sub-region that are opposite to each other at two sides of the display region along the first direction, the first sub-region includes a plurality of multiplexing unit groups and the second sub-region includes a plurality of test unit groups.

The pixel circuit includes a write-in compensation module for writing data signal(s) into a light emission device through a driving transistor and compensating a threshold voltage of the driving transistor; a first reset module for providing a signal of a first reset signal end to a gate of the driving transistor under control of a first reset control end; a second reset module for providing a signal of a second reset signal end to an anode of the light emission device under control of a second reset control end; and a light emission control module for connecting a drain electrode of the driving transistor with the anode under control of a light emission control end. A cathode of the light emission device is connected with a first power source voltage end; a potential of the first reset signal end is larger than a potential of the second reset signal end.

A display panel and a display device are provided. In the display panel, each composite pixel row includes a plurality of auxiliary sub-pixels disposed in a functional additional area and a plurality of main sub-pixels disposed in a main display area. Each of auxiliary pixel drive circuita is connected to a plurality of auxiliary sub-pixels. Each of main pixel drive circuits is connected to a corresponding main sub-pixel. A plurality of stages of gate drive circuits are correspondingly connected to the plurality of auxiliary pixel drive circuits and the plurality of main pixel drive circuits through a plurality of scanning signal lines to improve a display mismatch problem.

A display panel includes a base substrate, drive circuits, pixel circuits, and line groups. The drive circuits and the pixel circuits are arranged on the base substrate. The drive circuits provide control signals for the pixel circuits. The pixel circuits provide drive currents for light-emitting elements of the display panel. The drive circuits include a first drive circuit and a second drive circuit. The signal line groups include a first signal line group and a second signal line group. The first signal line group includes M signal lines that provide signals for the first drive circuit. The second signal line group includes N signal lines that provide signals for the second drive circuit, M≥1, and N≥1. The first drive circuit includes S1 level shift registers extending along a first direction. The second drive circuit includes S2 level shift registers extending along the first direction.

A current-selectable light-emitting-diode (LED) display includes pixels distributed in an array of rows and columns. The pixels are grouped in mutually exclusive clusters and cluster controllers are connected to each pixel in a cluster of pixels to control the pixels in the cluster to emit light. Each cluster controller comprises a selectable current source. Each of the selectable current sources can include cluster current sources that are responsive to a current-select signal to enable one or more of the cluster current sources. The pixels can include micro-LEDs and the cluster controller can be disposed between the micro-LEDs. The display can be disposed on a display substrate with signal wires. The signal wires can include separate wire segments that are electrically connected through regeneration circuits that regenerate the signals. The display can be an information display or a backlight.

An array substrate, a display panel and a display device are provided. The array substrate has a display area and a non-display area surrounding the display area. The array substrate includes: pixel circuits arranged in the display area in an array along a first direction and a second direction; a first gate driving circuit in the non-display area including first shift register units; and a second gate driving circuit in the non-display area including a plurality of second shift register units in cascade connection. The first gate driving circuit and the second gate driving circuit are electrically connected to different transistors in the pixel circuits; and an orthographic projection of the first gate driving circuit on a plane of the array substrate and an orthographic projection of the second gate driving circuit on the plane of the array substrate at least partially overlap along the second direction.

A display substrate includes: a base substrate having a display region and a peripheral region surrounding the display region; a plurality of sub-pixels in the display region; a plurality of data lines in the display region, electrically coupled to the plurality of sub-pixels respectively, and configured to provide a data signal to the plurality of sub-pixels respectively; a plurality of pads in the peripheral region, wherein at least a portion of the plurality of pads are configured to provide a data signal to the plurality of data lines respectively; at least one test data signal line in the peripheral region; at least one test control signal line in the peripheral region; and a plurality of test units in the peripheral region and on a side of the plurality of pads away from the display region.

A unit circuit constituting each stage of a shift register serving as a gate driver of a display device charges an internal node to an H level via a transistor T2 when an output signal G(n−4) of a preceding stage turns to the H level and sets the internal node to an L level via a transistor T3 when an output signal G(n+8) of a succeeding stage turns to the H level. Each of the unit circuits of last eight stages in the gate driver is provided with a transistor T4 including a gate terminal to which the signal G(n−4) is applied and a drain terminal connected to the internal node. A signal is applied to a source terminal of the transistor T4, the signal being at the H level during a period when the internal node of any of the last eight stages is to be set to the H level, and being the L level during the other periods. This suppresses a voltage fluctuation generated in the internal node when a stabilization circuit does not normally function.

A display panel and a display device are provided. The display panel and display device include gate driver on array (GOA) units in a first column, GOA units in a second column, and signal input lines. By adjusting a positional relationship between the signal input line and the GOA units in the first column and the GOA unit in the second column, the GOA units in the first column and the GOA units in the second column may share the signal input line, so as to save a set of signal input lines and reduce a width of the frame area.