A gate driver on array (GOA) circuit and a display panel are provided. The GOA circuit includes multi-stage cascaded GOA units, and each GOA unit includes a bootstrap module. The bootstrap effect of the bootstrap module is utilized to increase the gate voltage of the output transistor, which can effectively reduce the rise time and fall time of the scan signal output by each GOA unit, thereby improving the charging capability of the display panel.

An array substrate includes a base, a first conductive layer disposed at a side of the base, an insulating layer disposed at a side of the first conductive layer away from the base, and a second conductive layer disposed at a side of the insulating layer away from the first conductive layer. The insulating layer is provided with a first via hole exposing the first electrode of the first transistor and a second via hole exposing the first electrode of the second transistor. The second conductive layer includes a first conductive connection portion, and the first conductive connection portion connects the first electrode of the first transistor and the first electrode of the second transistor through the first via hole and the second via hole.

An output control unit of a shift register, a shift register and a driving method thereof, and a gate driving device. The output control unit includes N pull-up units, N pull-down units, and N signal output terminals. The n.sup.th pull-up unit is connected with a pull-up node, a high voltage source, an nth clock signal input terminal and an n.sup.th pull-down unit, the n.sup.th pull-down unit is connected to a pull-down node and a low voltage power source, and a connection point of the n.sup.th pull-up unit and the n.sup.th pull-down unit is further connected to the n.sup.th signal output terminal. The output control unit is configured to: provide clock signals from N clock signal input terminals to the N signal output terminals respectively under the control of a voltage of the pull-up node, and pull down levels of output signals of the N signal output terminals.

Disclosed is a shift register unit, including a first input circuit, an input control circuit, a pull-down control circuit, a pull-down circuit, an output circuit and a second input circuit. The first input circuit includes a first input sub-circuit, and is configured to, under control of the first signal input terminal, cause a voltage of the first voltage terminal to be output to a second terminal of the first input sub-circuit and output to the pull-up node via a first terminal thereof. The input control circuit is configured to pull down a potential of the second terminal to the potential of a first power supply voltage terminal under control of an enable signal terminal.

Disclosed is a display device including: a display panel; a timing controller generating image data corresponding to an input image, and generating and outputting a first start signal, an on clock, and an off clock; a level shifter generating a second start signal in synchronization with the first start signal, generating gate clocks that swing to a predetermined voltage and have multiple phases, by using the on clock and the off clock, and outputting the generated gate clocks; a shift register including multiple stages connected to gate lines of the display panel, respectively, and outputting a scan signal sequentially to the gate lines by using the second start signal and the gate clocks; and a data driving circuit supplying a data voltage corresponding to the image data to data lines of the display panel in synchronization with the scan signal.

A shift register unit, a gate line driving device includes multiple stages of the shift register units, and a driving method for being applied to the shift register unit; the shift register unit includes: an input module connected between an input terminal and a pull-up node, and configured to charge the pull-up node; an output module connected between the pull-up node, a first clock signal terminal and an output terminal, and configured to output to the output terminal a first clock signal received at the first clock signal terminal; a pull-up node reset module connected between a reset terminal, a pull-down node and the pull-up node, and configured to reset the pull-up node; and an output reset module connected between a second clock signal terminal, the pull-down node and the output terminal, and configured to reset the output terminal.

A touch display panel comprises a base substrate, a thin film transistor device structure, an organic light-emitting diode device structure, a packaging structure, and a touch screen structure that are sequentially arranged from bottom to top. The touch display panel further comprises a first induction electrode lead and a second induction electrode lead, wherein the first induction electrode lead is provided in the touch screen structure; the second induction electrode lead is provided in the thin film transistor device structure; and the first induction electrode lead is electrically connected to the second induction electrode lead.

A method and system for driving a light emitting device display is provided. The system provides a timing schedule which increases accuracy in the display. The system may provide the timing schedule by which an operation cycle is implemented consecutively in a group of rows. The system may provide the timing schedule by which an aging factor is used for a plurality of frames.

Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving circuit and a display device. The shift register unit comprises a latch module and a latch output module. Switching on and off of the transmission gates is controlled by using an intermediate signal generated based on a clock signal and an inputted signal, instead of by using the clock signal, such that the shift register unit will not be influenced by frequent flips of the clock signal in a non-operational state, thus avoiding a great deal of useless power consumption.

A liquid crystal display driving circuit comprising a scan control module, a gate driving signal output module and a stage transmission module. A voltage for controlling forward and reverse scan is inputted to the voltage level control input terminal of the scan control module; an output terminal of the scan control module outputs a scan control signal to the output control signal of the gate driving signal output module and the stage transmission module; the gate driving signal output module comprises first gate driving signal output submodule, a second gate driving signal output submodule and a first inverter; a CK1 signal is inputted to a clock input terminal of the first gate driving signal output submodule; a CK2 signal is inputted to a clock input terminal of the second gate driving signal output submodule; a CKV signal is inputted to a clock input terminal of the stage transmission module.