A display system circuitry capable of saving power consumption includes a display panel and a driver circuitry. In particular, the display panel includes a plurality of source electrodes with a plurality of data lines and a plurality of gate electrodes further includes a gate driver which is directly incorporated into a thin film transistor array to form Gate on Array (GOA) electrode, a source electrode transmitting a plurality of data driving signals, a gate electrode transmitting gate driving signals, a VCOM electrode transmitting voltage driving signals, a display electrode transmitting displaying driving signals. The driver circuitry includes a display driver IC which includes a source driver operably configured to drive the source electrode and gate control to control gate driver output, and a touch driver IC configured to generate the touch scan signal from a touch sensor.

A unit circuit of a shift register includes an output transistor whose control terminal is connected to a first node, first and second set transistors, first and second reset transistors, a control signal generating circuit that generates a control signal that changes to an on level when a first clock signal changes to an on level while the potential of the first node is at an off level, and that outputs the generated control signal to the unit circuits at a preceding stage and a next stage, a transistor that applies an off-level potential to the first node based on a control signal output from the unit circuit at the preceding stage, and a transistor that applies an off-level potential to the first node based on a control signal output from the unit circuit at the next stage.

A display apparatus includes a display panel configured to display an image. A gate driver is configured to output a plurality of gate signals to the display panel. A data driver includes a first area and a second area. The first area of the data driver includes a first channel group configured to output first data voltages in a first output sequence. The second area of the data driver includes a second channel group configured to output second data voltages in a second output sequence opposite to the first output sequence.

To solve the problems of complicated wiring and color difference between LED lamps in adjacent lines in the prior art, the application provides a driver chip, an LED lamp and an LED display screen. On the one hand, the application provides an LED lamp, which further comprises a data direction judgment & switch module arranged inside or outside the driver chip and connected with the driving module; The two signal ends of the LED lamp provided by the application can input and output data signals without distinguishing data directions. Judging the data signal directions of the first signal end and second signal end by the data direction judgment & switch module, automatically switching the input end and output end of the data signals, the wiring complexity is greatly reduced. And there is no color difference among the LED lamps in adjacent rows or columns.

Disclosed are a backlight module, a control method therefor and a display device, a driving method therefor. A backlight source is divided into light-emitting areas, and a current control circuit for driving the light-emitting area to emit light is configured for each light-emitting area. The light-emitting areas in the backlight module are arranged in one-to-one correspondence to the current control circuits.

A display panel includes a source driving circuit, a multiplexer circuit, and multiple sub-pixels arranged in an array. The multiplexer circuit is configured to, under the control of a first multiplexing signal to an Nth multiplexing signal, control the source driving circuit to be connected with sub-pixels of one or more columns; and in a jth frame, a multiplexing signal turn-on sequence for sub-pixels of an odd row is from a Jth multiplexing signal to sequentially increasing to the Nth multiplexing signal and from the first multiplexing signal to sequentially increasing to a (J−1)th multiplexing signal, and a multiplexing signal turn-on sequence for sub-pixels of an even row is completely opposite to the multiplexing signal turn-on sequence for the sub-pixels of the odd row.

A display device according to the present disclosure includes: a pixel array unit (30) in which pixel circuits (20A) are disposed in a matrix form, the pixel circuits each including a light emission unit (21), a write transistor (23) that writes a signal voltage (Vsig) of a video signal, a retention capacitor (24) that retains the signal voltage (Vsig) written by the write transistor (23), a drive transistor (22) that drives the light emission unit (21) on the basis of the signal voltage (Vsig) retained by the retention capacitor (24), and an auxiliary capacitor (25) of which one terminal is connected to a source node of the drive transistor (22); and a control unit (90) that provides a potential change to a source electrode of the drive transistor (22) by coupling through the auxiliary capacitor (25) to set an operation point of the drive transistor (22) as a cut-off region after the threshold value correction process.

A shift register unit, a driving method thereof, a gate driving circuit, and a display device are provided. The shift register unit includes an input branch and a reset branch; the input branch is configured to form or disconnect a first path between a first scan voltage terminal and a pull-up node under control of a potential of a first control terminal. The reset branch is configured to form or disconnect a second path between a second scan voltage terminal and the pull-up node under control of a potential of a second control terminal.

A display device includes a first direction, a plurality of pixels arranged in a second direction intersecting the first direction, at least one scanning signal line connected to the plurality of pixels, a scanning signal line driving circuit connected to the scanning line, the scanning signal line driving circuit includes a switch for outputting a signal to the scanning signal line, a first power supply line for providing a first voltage to the switch, a second power supply line for providing a second voltage smaller than the first voltage to the switch, and the switch is provided between the first power supply line and the second power supply line, a line width of the second power supply line is 4 times the line width of the first power supply line or more and 40 times the line width of the first power supply line or less.

A gate driver is constituted of a first gate driver including a first shift register that is configured by bistable circuits corresponding to gate bus lines on odd-numbered lines arranged on one side of a display portion, and a second gate driver including a second shift register that is configured by bistable circuits corresponding to gate bus lines on even-numbered lines arranged on another side of the display portion. A first buffer circuit is provided on one end side of each gate bus line, and a second buffer circuit is provided on another end side of each gate bus line. A control signal for controlling the scanning order of the gate bus line is given to the bistable circuit and the second buffer circuit.