Patent classifications
G09G2310/0283
Scan driving circuit and driving method thereof, and display device
A scan driving circuit and a driving method thereof, and a display device are disclosed. The scan driving circuit includes: a control circuit, a scanning circuit group and a first processing circuit group. The control circuit is configured to generate and output a keyword signal to the first processing circuit group, to control a scan order of respective scanning circuits in the scanning circuit group; the first processing circuit group is configured to generate a scan enable signal according to the keyword signal, and output the scan enable signal to a scanning circuit corresponding to the keyword signal in the scanning circuit group.
MULTI-DISPLAY DEVICE, DISPLAY DEVICE, METHOD FOR CONTROLLING MULTI-DISPLAY DEVICE, AND METHOD FOR CONTROLLING DISPLAY DEVICE
A multi-display device has a plurality of display devices are arranged in a matrix shape. Each of the display devices includes: a scanning signal line drive circuit configured to switch a scanning direction of scanning signal lines of the corresponding display device between upward and downward for each row according to a position at which the corresponding display device is disposed; and a control unit configured to control the scanning signal line drive circuit such that one of the upward and downward directions of the scanning direction is selected as a first direction and the scanning signal lines are sequentially driven in the selected first direction and to control the scanning signal line drive circuit such that a second direction which is opposite to the selected first direction is selected and the scanning signal lines are sequentially driven in the selected second direction whenever a predetermined period elapses.
Shift register and driving method thereof, gate driving circuit and display apparatus
There are provided in the present disclosure a shift register and a driving method thereof, a gate driving circuit and a display apparatus. The shift register of the present disclosure includes: a forward scanning input sub-circuit for pre-charging a potential of a pull-up node by an operation level signal under control of a forward input signal and a forward scanning signal upon scanning forwards; a backward scanning input sub-circuit for pre-charging the potential of the pull-up node by an operation level signal under control of a backward input signal and a backward scanning signal upon scanning backwards; an output sub-circuit for outputting a clock signal through a signal output terminal under control of the potential of the pull-up node; wherein the pull-up node is a connection node of the forward scanning input sub-circuit, the backward scanning input sub-circuit and the output sub-circuit.
SHIFT REGISTER CIRCUIT
A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
SCANNING DRIVE CIRCUIT, DRIVING METHOD, DISPLAY PANEL, AND DISPLAY APPARATUS
A scanning drive circuit, a driving method, a display panel, and a display apparatus are provided. The scanning drive circuit includes 1.sup.st to n.sup.th shift registers cascaded sequentially. Each shift register includes a pull-down unit, a pull-up unit, and first and second output units. The first output unit is electrically connected to a second supply voltage terminal and a first clock signal output terminal, and configured to output a level to a first output terminal based on levels of a second node and a third node. The second output unit is electrically connected to a third supply voltage terminal and a second clock signal output terminal, and configured to output a level to a second output terminal based on the levels of the second node and a fourth node. The first and the second output terminals of each shift register output effective levels sequentially.
Driving system and method of touch display panel
A driving system of touch display panel includes a panel having an active area, a left gate driving circuit and a right gate driving circuit. The left gate driving circuit is disposed on the left side of the active area, and is connected with a plurality of left gate lines to provide gate driving voltages for performing driving in a scanning direction. The right gate driving circuit is disposed on the right side of the active area, and is connected with a plurality of right gate lines to provide gate driving voltages for performing driving in a scanning direction. The scanning direction in which the left gate driving circuit performs driving is opposite to that in which the right gate driving circuit performs driving.
Array substrate, driving method thereof, display device
An array substrate, a driving method thereof, and a display device are provided. The array substrate comprises a display area and a peripheral area. The display area includes a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction. The peripheral area includes a source driver on a side of the peripheral area along the second direction. The display area includes an opening, a first display area on a side of the opening away from the source driver, and a second display area adjacent to the first display area along the first direction. Data lines in the first display area are connected in one-to-one correspondence with data lines in the second display area, and gate lines in the first display area and gate lines in the second display area are disconnected from each other.
SHIFT REGISTER UNIT AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE
Disclosed is a shift register unit, including a first input circuit, an input control circuit, a pull-down control circuit, a pull-down circuit, an output circuit and a second input circuit. The first input circuit includes a first input sub-circuit, and is configured to, under control of the first signal input terminal, cause a voltage of the first voltage terminal to be output to a second terminal of the first input sub-circuit and output to the pull-up node via a first terminal thereof. The input control circuit is configured to pull down a potential of the second terminal to the potential of a first power supply voltage terminal under control of an enable signal terminal.
Shift register, driving method thereof, gate driver circuit and display device
The present disclosure provides a shift register, a driving method thereof, a gate driver circuit and a display device. The shift register includes a first control module, a scanning control module and a first output module.
SHIFT REGISTER UNIT AND DRIVING METHOD THEREOF, GATE DRIVE CIRCUIT AND DISPLAY DEVICE
A shift register unit and a driving method thereof, a gate drive circuit, and a display device are disclosed. The shift register unit includes a first input sub-circuit, a first control sub-circuit, an output sub-circuit, and a second control sub-circuit. The first input sub-circuit is configured to output a first control signal of the first control signal terminal to the first control sub-circuit; the first control sub-circuit is configured to output a second input signal of the second input terminal to the first node, or the first control sub-circuit is configured to output the second input signal to the second control sub-circuit; the second control sub-circuit is configured to output a second clock signal to the second node; or the second control sub-circuit is configured to output a first voltage of the first voltage terminal to the second node under control of a level of the control node.