The present application discloses a gate driver control circuit including an encoder configured to encode instruction information to obtain a coded instruction and to transmit the coded instruction. The gate driver control circuit further includes a decoder coupled to the encoder and configured to decode the coded instruction to obtain the instruction information. Additionally, the gate driver circuit includes at least one multiplexer coupled to the decoder. Each multiplexer is configured to receive a first set of multiple timing-control signals and the instruction information, to adjust the first set of multiple timing-control signals to a second set of multiple timing-control signals based on the instruction information, and to output the second set of multiple timing-control signals. The gate driver control circuit further includes at least one gate-array sub-circuit. Each gate-array circuit is configured to output multiple row-scanning signals in response to the second set of multiple timing-control signals.

A shift register unit and a driving method thereof, a gate drive circuit and a display device. The shift register unit includes a first input circuit, an output circuit and a first output pull-down circuit. The first input circuit is configured to charge a pull-up node in response to a first clock signal and reset the pull-up node in response to the first clock signal; the output circuit is configured to output a second clock signal to an output terminal under a control of a level of the pull-up node; the first output pull-down circuit is configured to denoise the output in response to a third clock signal.

A display device according to the present disclosure includes: a pixel array unit (30) in which pixel circuits (20A) are disposed in a matrix form, the pixel circuits each including a light emission unit (21), a write transistor (23) that writes a signal voltage (Vsig) of a video signal, a retention capacitor (24) that retains the signal voltage (Vsig) written by the write transistor (23), a drive transistor (22) that drives the light emission unit (21) on the basis of the signal voltage (Vsig) retained by the retention capacitor (24), and an auxiliary capacitor (25) of which one terminal is connected to a source node of the drive transistor (22); and a control unit (90) that provides a potential change to a source electrode of the drive transistor (22) by coupling through the auxiliary capacitor (25) to set an operation point of the drive transistor (22) as a cut-off region after the threshold value correction process.

Disclosed are a backlight module, a control method therefor and a display device, a driving method therefor. A backlight source is divided into light-emitting areas, and a current control circuit for driving the light-emitting area to emit light is configured for each light-emitting area. The light-emitting areas in the backlight module are arranged in one-to-one correspondence to the current control circuits.

A gate scanning unit circuit is applied in a display panel including a number of gate lines and a driver configured to output clock signals. The gate scanning unit circuit is configured to scan the number of gate lines. The gate scanning unit circuit includes a flip-flop and at least two output units. The flip-flop is configured to output a trigger signal. Each output unit is connected to the flip-flop and the driver. Each of the at least two output units is connected to the number of gate lines one-to-one. The output unit is configured to output a gate scan signal to the corresponding connected gate line according to the trigger signal and the clock signals.

A shift register and driving method thereof, a gate driving circuit and a display device are provided. The shift register includes a first input unit, a second input unit, a pull-up control unit, a pull-down control unit, an output control unit and an output reset unit, wherein the first input unit, the second input unit, the pull-up control unit, the pull-down control unit and the output control unit are coupled to a first node, and the pull-up control unit, the pull-down control unit and the output reset unit are coupled to a second node.

A shift register and driving method thereof, a gate driving circuit and a display device are provided. The shift register includes a first input unit, a second input unit, a pull-up control unit, a pull-down control unit, an output control unit and an output reset unit, wherein the first input unit, the second input unit, the pull-up control unit, the pull-down control unit and the output control unit are coupled to a first node, and the pull-up control unit, the pull-down control unit and the output reset unit are coupled to a second node.

A display apparatus includes a display panel configured to display an image. A gate driver is configured to output a plurality of gate signals to the display panel. A data driver includes a first area and a second area. The first area of the data driver includes a first channel group configured to output first data voltages in a first output sequence. The second area of the data driver includes a second channel group configured to output second data voltages in a second output sequence opposite to the first output sequence.

A gate driver on array (GOA) circuit and a display panel are provided. The GOA circuit includes multi-stage cascaded GOA units, and each GOA unit includes a bootstrap module. The bootstrap effect of the bootstrap module is utilized to increase the gate voltage of the output transistor, which can effectively reduce the rise time and fall time of the scan signal output by each GOA unit, thereby improving the charging capability of the display panel.

A display panel includes a scan driving circuit, signal pins and a first gating circuit. Signal pins include a detection signal pin and an enable signal pin. The scan driving circuit includes scan drive units disposed in a cascade manner. The first gating circuit includes a first switch unit and a second switch unit. An input terminal of the first switch unit is electrically connected to a scan signal detection terminal of an Nth-stage scan drive unit. An input terminal of the second switch unit is electrically connected to a scan signal detection terminal of a first-stage scan drive unit. An output terminal of the first switch unit and an output terminal of the second switch unit are both electrically connected to the detection signal pin. The first switch unit is configured to turn on in a forward scan detection stage and turn off in a backward scan detection stage. The second switch unit is configured to turn on in the backward scan detection stage and turn off in the backward scan detection stage.