A pixel includes a pixel circuit and an organic light emitting diode. The pixel circuit has first, second, third, and fourth transistors. The first transistor controls an amount of current flowing from a first driving power supply coupled to a first node to a second driving power supply through the organic light emitting diode. The turns on when a scan signal is supplied to a first scan line. The third transistor turns on when a scan signal is supplied to a second scan line. The fourth transistor turns on when a scan signal is supplied to a third scan line. The first transistor is a p-type Low Temperature Poly-Silicon thin film transistor and the third transistor and the fourth transistor are n-type oxide semiconductor thin film transistors.

A pixel includes a plurality of transistors and an organic light emitting diode. The transistors include a first transistor to control an amount of current flowing to the organic light emitting diode. Additional transistors are connected to the first transistor or the organic light emitting diode. The first transistor is a Low Temperature Poly-Silicon (LTPS) thin film transistor. One or more of the other transistors are oxide semiconductor transistors.

A touch sensor integrated type display device includes: a display panel including: pixels connected to data lines and gate lines and division-driven into a plurality of panel blocks, and a plurality of touch sensors connected to the pixels, a display driving circuit providing data of an input image to the pixels in multiple display periods divided from one frame period, and a touch sensing circuit driving the touch sensors and sensing a touch input in a touch sensing period allocated between the display periods of the frame period, adjacent panel blocks being division-driven in the display periods that are separated from each other with the touch sensing period, in which the touch sensors are driven, interposed therebetween, the display driving circuit including a shift register: shifting a gate pulse in accordance with a shift clock timing, and sequentially supplying the gate pulse to the gate lines.

A display module including a substrate having a plurality of pixels, a data line that supplies a data signal to a pixel, a current supply line that supplies electric current to the pixel, a data driving circuit that supplies a data signal to the data line, and a gate driving circuit thereon. The plurality of pixels are arranged in a display area of the substrate, and each of the plurality of pixels includes a light emitting device, a first thin film transistor connected to the data line that supplies the data signal, a second thin film transistor connected to the current supply line, and a capacitor. The light emitting device includes a first electrode layer connected to the second thin film transistor, an organic layer formed on the first electrode layer, and a second electrode layer formed on the organic layer.

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.

A display apparatus includes a display panel having a plurality of gate lines, a plurality of data lines, and a plurality of subpixels. Each of the plurality of subpixels includes a subpixel electrode connected to one of the plurality of gate lines and one of the plurality of data lines through a switching element. A gate driver is configured to output a plurality of gate signals to the plurality of gate lines and to deactivate at least one of the plurality of gate signals in a P-th frame. A data driver is configured to output a plurality of data voltages to the plurality of data lines. Here, P is a positive integer.

A shift register unit and a driving method thereof, a gate driving circuit, and a display device are provided. In the shift register unit, the input circuit inputs an input signal to a first node; the output circuit outputs an output signal to an output terminal; the first control circuit performs a first control on a level of a first control node; the first noise reduction control circuit controls a level of a second node; the second control circuit performs a second control on a level of a second control node; the second noise reduction control circuit controls a level of a third node; the first voltage-stabilizing circuit performs a third control on the level of the second control node, and the second control and the third control cause at least part of the second noise reduction control circuit to be in different bias states.

A mask, a display panel, and an electronic equipment are provided. The mask allows an opening pattern to be moved to a side of a repeat region. Based on this structure, the display panels with the same resolution and different sizes may use the masks with the same size, and differences between these masks are merely different distances between the opening patterns and edges of the repeat regions, thus solving at least one technical problem existing in conventional 8K electronic equipment that the masks with the different sizes require to be manufactured for the display panels with the different sizes.

A gate driving circuit includes a plurality of unit stages connected to each other, wherein each of the plurality of unit stages includes a first transistor having a lower gate electrode, an upper gate electrode disposed on the lower gate electrode, an active layer disposed between the lower gate electrode and the upper gate electrode, a first electrode contacting a first portion of the active layer, and a second electrode contacting a second portion of the active layer, a first capacitor defined by a first region in which the lower gate electrode and the upper gate electrode overlap, and a second capacitor defined by a second region in which the upper gate electrode and the first electrode overlap, wherein the upper gate electrode and the lower gate electrode are electrically coupled to each other in the first region where the upper gate electrode and the lower gate electrode overlap to form the first capacitor.

A display device includes: a substrate including first and second display regions and first and second non-display regions; a plurality of first pixels in the first display region; a plurality of second pixels in the second display region; a plurality of first scan stage circuits in the first non-display region, the first scan stage circuits configured to provide a scan signal to the first pixels; a plurality of second scan stage circuits in the second non-display region, the second scan stage circuits configured to provide a scan signal to the second pixels; a plurality of dummy scan stage circuits in the second non-display region, the dummy scan stage circuits being between the second scan stage circuits; and a scan bridge line in the second non-display region, the scan bridge line connecting one second scan stage circuit among the second scan stage circuits and a dummy scan stage circuit adjacent thereto.