A display device including a display panel configured to display an image, a data driver configured to supply a data voltage to the display panel and having a precharge circuit configured to perform a precharging operation, and a timing controller configured to control the data driver, wherein the charge circuit generates a precharge voltage based on a precharge signal supplied in a horizontal blank period and is controlled to output or not output the precharge voltage based on a precharge selection signal.

The present embodiments disclose a display device. A display device according to an embodiment of the present disclosure comprises a pixel unit including a plurality of pixels, each including a luminous element and a pixel circuit connected to the luminous element, a clock generator configured to generate a plurality of clock signals each corresponding to each of a plurality of subframes constituting a frame, and a parallel to serial converter configured to convert the plurality of clock signals to a serial clock signal and transfer the serial clock signal to the pixel unit, and wherein the pixel circuit of each pixel includes a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of the plurality of subframes and a second pixel circuit configured to store bit values of image data in the frame and generate the control signal based on the stored bit values and the serial clock signal such that each subframe included in the frame is controlled according to each bit value.

A driving chip includes a data channel block including a plurality of data channels, a scan channel block disposed in a first direction from the data channel block and including a plurality of scan channels, a data pad block disposed outside the data channel block and the scan channel block in the first direction and including a plurality of data pads which respectively receive a data signal from the plurality of data channels, and a scan pad block disposed outside the data channel block and the scan channel block in the first direction, disposed outside the data pad block in a second direction crossing the first direction and including a plurality of scan pads which respectively receive a scan signal from the scan channels.

Provided is a display driving circuit including a plurality of source channels configured to provide data voltages to a plurality of data lines of a display panel, respectively; a dummy channel on one side of at least one of the source channels; and control logic configured to control operations of the source channels and the dummy channel, wherein, when failure of a first source channel from among the source channels is determined, the control logic is further configured to provide data voltages to data lines corresponding to the first source channel and second source channels, respectively, which are between the first source channel and the dummy channel, by using the second source channels and the dummy channel.

A display panel, a display device including the display panel, and a personal immersive system using the display device includes a sample & holder that sequentially samples a data voltage sequentially outputted from a demultiplexer and then simultaneously output the data voltage to a plurality of data lines, and sub-pixels that sequentially charge the data voltage inputted from the sample & holder in response to a scan pulse.

The present application discloses an over-current protection method for display panel and a display device. The over-current protection method for display panel includes the following steps: calculating current input by a level shifter during a first preset time of a first clock signal after the first clock signal is received; determining whether the current input by the level shifter during the first preset time is larger than a first preset current; controlling the level shifter to stop running in determining that the current input by the level shifter during the first preset time is larger than the first preset current.

A display device includes a display panel including a plurality of pixels which are connected to a plurality of gate lines and a plurality of data lines and display a plurality of consecutive frames of images, a data driver driving the data lines, a gate driver driving the gate lines, a clock generator outputting a gate clock signal, which drives the gate driver and swings between a gate-on voltage and a gate-off voltage, and a signal controller outputting a gate pulse signal which drives the clock generator and a data control signal which controls the data driver. The clock generator includes a voltage maintainer maintaining the gate clock signal at a reference voltage that has a fixed value between the gate-on voltage and the gate-off voltage for a predetermined time.

Provided are a display panel and a display device. The display panel includes rows of pixels and a gate driver circuit; where a pixel among the plurality of rows of pixels includes a pixel circuit and the pixel circuit includes a light emission control terminal and a first scan drive terminal; the gate driver circuit includes stages of light emission drive devices, where each of the plurality of stages of light emission drive devices is disposed in correspondence to at least one row of pixel circuits and configured to provide a light emission control signal to the light emission control terminal of the pixel circuit; and the gate driver circuit further includes at least one stage of first scan drive device, where an input terminal of the first scan drive device is connected to an output terminal of the light emission drive device.

A display device may include a timing controller, a level shifter, a gate driver, and a display panel. The timing controller may generate a first on-clock signal, a first off-clock signal, and a first output control signal. The level shifter may generate a first-type gate clock signal. A rising edge of the first-type gate clock signal and a falling edge of the first-type gate clock signal may be respectively synchronized with a rising edge of the first on-clock signal and a falling edge of the first off-clock signal. The gate driver may output first-type gate signals based on the first-type gate clock signal. The display panel may include pixels. The pixels may emit lights in response to the first-type gate signals. The level shifter may partially block a pulse of the first-type gate clock signal based on the first output control signal to generate sub-pulses.

A display apparatus includes an integral integrated circuit and a display panel. The integral integrated circuit includes a gate channel which outputs a gate primitive signal and a data channel which outputs a data voltage. The display panel includes a level shifter which amplifies the gate primitive signal to generate a gate signal. The display panel is configured to display an image based on the gate signal and the data voltage. The display panel includes a first gate line extending in a first direction and a second gate line extending in a second direction. The second direction is different from the first direction. The second gate line is connected to the first gate line. The level shifter is connected to the second gate line.