A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.

Display panel redundancy schemes and methods of operation are described. In an embodiment, and display panel includes an array of drivers (e.g. microdrivers), each of which including multiple portions to independently receive control and pixel bits. In an embodiment, each driver portion is to control a group of redundant emission elements.

A method for compensating for a difference between positive and negative polarities of a display panel is provided. The display panel is electrically connected to a source driver, and the source driver includes first and second output drivers alternately connected to a same data line in the display panel. The method may include: detecting positive and negative polarity effective voltages of the display panel; adjusting a driver setting of at least one of the first and second output drivers based on the positive and negative polarity effective voltages, to change magnitudes of the positive and/or negative polarity effective voltages; and when the positive and negative polarity effective voltages relative to a common mode voltage are same in absolute value, obtaining an adjusted driver setting and applying the adjusted driver setting to the at least one of the first and second output drivers.

A semiconductor device including a substrate, and a first circuit supported by the substrate and including a plurality of TFTs including a first TFT, wherein the first TFT includes a semiconductor layer, a lower gate electrode located on a side of the substrate of the semiconductor layer and overlapping a part of the semiconductor layer via a lower gate insulating layer, and an upper gate electrode located on a side opposite to the substrate of the semiconductor layer and overlapping a part of the semiconductor layer via an upper gate insulating layer, one of the lower gate electrode and the upper gate electrode is a first gate electrode and the other is a second gate electrode, a first signal is supplied to the first gate electrode, and a second signal different from the first signal is supplied to the second gate electrode, the first TFT has a threshold voltage between a high-level potential and a low-level potential of the first signal and between a high-level potential and a low-level potential of the second signal, and a period during which the first signal is at the high-level potential and a period during which the second signal is at the high-level potential do not overlap each other.

Disclosed are a gate driver and a display panel including the same. The gate driver according to an embodiment includes a plurality of signal transfer units cascade-connected via a carry line to which a carry signal is applied from a previous signal transfer unit, and an n.sup.th (n is a positive integer) signal transfer unit includes a first output unit configured to output a first gate signal to a first output node according to a voltage of a first control node configured to pull up an output voltage and a second control node configured to pull down the output voltage; and a second output unit configured to output a second gate signal in which a phase of the first gate signal is reversed to a second output node, wherein the second output unit may include a first pull-up transistor configured to output a high potential voltage to the second output node according to a voltage of a second control node of an (n-i).sup.th (i is a positive integer less than n) signal transfer unit; and a second pull-down transistor configured to output a first low potential voltage to the second output node according to a voltage of a first control node of an (n+j).sup.th (j is a natural number greater than n) signal transfer unit.

A gamma reference voltage generator includes a first resistor string, black voltage setters, a selector, and a second resistor string. The first resistor string receives a first reference voltage and a second reference voltage. The black voltage setters extract a plurality of black candidate voltages from the first resistor string. The selector selects one of the black candidate voltages as a black gamma voltage based on a selection signal. The second resistor string receives a first voltage corresponding to one of the black candidate voltages and a second voltage extracted from the first resistor string. In addition, the gamma reference voltage generator includes gamma voltage setters that extract a plurality of gamma voltages from the second resistor string.

A display device can include a display panel having a plurality of pixels disposed on a substrate, and a power supplier configured to supply a driving voltage to the display panel. The power supplier can include a first converter configured to receive an input voltage supplied from an external system and convert the input voltage into a boost voltage, a second converter configured to convert the boost voltage into the driving voltage, a first feedback unit configured to output a first pulse width modulation (PWM) signal to the first converter so that the boost voltage is proportional to a first reference voltage, and a second feedback unit configured to output a second PWM signal to the second converter so that the driving voltage is proportional to a second reference voltage.

A semiconductor device includes a semiconductor substrate including an active region defined in a well impurity layer having a first conductivity type, a gate electrode on the active region, and a gate insulating layer between the gate electrode and the active region. The active region includes a source region and a drain region at sides of the gate electrode, the source region and the drain region having a second conductivity type, a channel region between the source and drain regions, the channel region having the first conductivity type, a first halo region in contact with the source region and a second halo region in contact with the drain region, the first halo region and the second halo region having the first conductivity type, and a slit well region between the first and second halo regions, the slit well region having the first conductivity type.

Provided are a gate driving circuit and a display device including the same. The gate driving circuit includes a first controller configured to control a first control node to act as a pull-up control node to turn on a first transistor when an activation clock is input to the first controller for a first unit time, and to be deactivated when a deactivation clock is input thereto for a second unit time; and a second controller configured to control a second control node to act as a pull-up control node to turn on a second transistor when the activation clock is input to the second controller for the second unit time, and to be deactivated when the deactivation clock is input thereto for the first unit time.

A display device includes a display panel configured to display an image, a timing controller configured to control the display panel, a memory operating in association with the timing controller, and a data transmission/reception circuit configured to write data to the memory or to read data from the memory under the control of the timing controller, wherein the data transmission/reception circuit includes a transmission direction setting unit configured to set a data transmission/reception path depending on a data transmission period or a data reception period in order to avoid collision between input and output during data transmission/reception.