A scan driver includes stages, each of the stages receiving first and second clock signals having a first low level as an active level, and a third clock signal having a high level as the active level. Each of the stages includes a logic circuit that changes a voltage of a first node to the first low level based on an input signal and the first clock signal, and changes a voltage of the first node to a second low level lower than the first low level based on the second clock signal, a first output buffer that outputs, as an active-low scan signal, the second clock signal in response to the voltage of the first node, and a second output buffer that outputs, as an active-high scan signal, the third clock signal in response to the voltage of the first node.

Provided is an organic light-emitting display panel. Pixel-driving circuits of subpixels in a same row of pixel units are connected to a same light emission control signal line. The pixel-driving circuits of the subpixels in the same row of pixel units are connected to a same reset control signal line; and an anode of a light-emitting element of each of the subpixels to which the pixel-driving circuits electrically connected to the reset control signal line belong is at a reset voltage. In a display period of each frame of image, in at least part of a period during which an i-th row of pixel units are in a light emission stage, anodes of light-emitting elements of a j-th row of pixel units are at a reset voltage; and the j-th row of pixel units and the i-th row of pixel units are adjacent two rows of pixel units.

The present disclosure provides a display panel and a display device. The display panel includes source driver chips. The source driver chips include charging compensation modules, and each of the charging compensation modules includes: a plurality of shift registers cascadely connected and configured to time-divisionally output a plurality of pulse signals, and a plurality of level shift circuits time-divisionally conducted in response to the plurality of the pulse signals to prevent the plurality of the level shift circuits in the source driver chips from outputting and generating a plurality electron currents at a same time, which would result in a superposition of current peaks and cause electromagnetic interference problems.

A power voltage generator includes a charge pump and a regulator. The charge pump generates a charge pumping voltage. The charge pumping voltage has a headroom margin which is automatically set. The charge pumping voltage is varied based on a target voltage. The regulator generates a power voltage based on the charge pumping voltage.

The present disclosure relates to a touch driver circuit capable of reducing the distortion of a common voltage modulation signal caused by line resistance. The touch driver circuit may include a touch power integrated circuit configured to generate a reference gamma voltage set to output the reference gamma voltage set through a gamma transmission path during a display period, and generate a touch driving voltage to output the touch driving voltage through the gamma transmission path during a touch period, and a source-readout integrated circuit configured to drive a source driving circuit block using the reference gamma voltage set during the display period, and generate a common voltage modulation signal using the touch driving voltage to drive a readout circuit block using the generated common voltage modulation signal during the touch period.

A display device can include a display panel having sub pixels configured to emit light of different colors, a data driver configured to output a data voltage to the sub pixels via data lines, and a timing controller configured to output power control signals for controlling a driving current which drives the data driver. The data driver can include source driving integrated circuits, each including power control circuits configured to generate the driving current in accordance with each of the power control signals, and amplifiers configured to be applied with the driving current to output the data voltage to each of the data lines.

A control system includes a plurality of driving circuits coupled in series, which include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a first flag signal selector. The first transmitter is coupled to the first receiver, and the first flag signal selector is coupled between the first receiver and the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver, a second transmitter and a second flag signal selector. The second transmitter is coupled to the second receiver, and the second flag signal selector is coupled between the second receiver and the second transmitter.

Disclosed is an LED display device, a driving method and a chip thereof. The LED display device comprises: a display array comprising row lines, column lines, and pixel units each comprising an LED connected to a corresponding one of the row lines and a corresponding one of the column lines; a row driver module, connected to the row lines and providing selection signals; a column driver module, connected to the column lines and providing driving signals corresponding to gray scale data according to pulse width modulation signals; a channel control module, connected to the column lines and adjusting a column-line voltage of a corresponding column line to a target voltage in a first time period when a corresponding pulse width modulation signal is active, thus improving constant current cut-in speed and improve consistency and linearity under low gray scale when an image with low gray scale is displayed.

A display panel includes an array of pixels extending in a plane and arranged in rows, wherein a first plurality of the rows extend to an edge of the pixel array and one or more rows at a corner of the pixel array are recessed from the edge. The display panel includes driver circuits each connected to a corresponding row of the pixel array and occupying an area in the plane, the area having a long dimension and an orthogonal short dimension. A first set of driver circuits are connected to corresponding rows of the first plurality of rows and a second set of driver circuits are connected to corresponding rows at the corner of the pixel array. The long dimension of each of the drivers of the first set of drivers is greater than the long dimension of each of the drivers of the second set of drivers.

A display device includes a display panel including data lines and pixels electrically connected to the data lines. The data driver supplies data signals to the data lines. The data driver includes: a first output buffer electrically connected to a first data line of the data lines, the first output buffer outputting a first data signal to the first data line; and a first comparator electrically connected to an output terminal of the first output buffer, the first comparator comparing a first slew rate of the first data signal with a first reference slew rate.