A display device can include a light emitting element, and a pixel driving circuit connected to the light emitting element and configured to include first to fourth nodes. The pixel driving circuit can include a driving transistor connected to the first to third nodes, a plurality of switching transistors, and a storage capacitor. Among the plurality of switching transistors, the switching transistor connected to a source node of the driving transistor is controlled by a second scan signal, and is configured to apply a data voltage to the source node of the driving transistor. The second scan signal can be applied one or more times during one frame.

An embodiment provides a latch circuit which outputs, to a digital analog converter (DAC), a digital signal including grayscale data, the latch circuit including a first latch configured to store the digital signal and a second latch configured to output the digital signal by controlling first timing at which a level of a first signal included in the digital signal becomes an enable level, based on a center grayscale. The grayscale data includes first grayscale data and second grayscale data.

A display device includes: a display panel on which a plurality of pixels are disposed; a timing controller configured to receive Nth frame data and (N+1)th frame data and output a luminance control signal; and a power supply configured to output a reference voltage from a plurality of reference voltages each having a different level in response to the luminance control signal, in which output luminance of the plurality of pixels is determined according to the level of the reference voltage thereby maximizing an HDR effect.

Disclosed is a display device comprising a light emitting element, and a pixel driving circuit connected to the light emitting element and configured to include first to fourth nodes, wherein the pixel driving circuit includes a driving transistor connected to the first to third nodes, a plurality of switching transistors, a storage capacitor, and a plurality of signals and voltage lines, wherein an initialization voltage applied through an initialization line among the plurality of signals and voltage lines is varied based on a data voltage.

A display apparatus includes a display panel including a sub-display area including an opening and a main display area including no opening, a gate driver supplying a gate signal to the display panel, and a driver controlling the gate driver, wherein the driver separates a sub-clock signal for controlling the sub-display area and a main clock signal for controlling the main display area and varies a pulse width of the sub-clock signal.

The disclosure relates to a disclosed display device and a display driving method. According to an embodiment, the disclosed display device may include a display panel having a first subpixel including a light emitting element and being connected to a sensing line in the display panel for sensing a characteristic value of the first subpixel; a gate driving circuit configured to supply a scan signal to the first subpixel through a gate line in the display panel; a data driving circuit configured to supply a data voltage to the first subpixel through a data line in the display panel; and a timing controller. The timing controller may be configured to: control the gate driving circuit; determine compensation data for compensating for a deviation in the characteristic value of the first subpixel based on a first sensing voltage, a second sensing voltage, and a third sensing voltage on the sensing line; and control the data driving circuit based on the compensation data.

A sensing circuit includes a first input selecting circuit connected to a first sensing line and a second sensing line, a first path setting circuit that sets a path of a first sensing signal received from the first sensing line or a path of a second sensing signal received from the second sensing line, a second path setting circuit that sets a path of a sensing reference voltage, a first switch matrix connected to the first path setting circuit and the second path setting circuit, a first mode setting circuit connected to a first output terminal of the first switch matrix, a first common sensing amplifier connected to the first mode setting circuit, a second mode setting circuit connected to a second output terminal of the first switch matrix, and a second common sensing amplifier connected to the second mode setting circuit.

An overcurrent protection circuit includes: a sampling sub-circuit configured to acquire gate input signals, select a gate input signal with a voltage value greater than a first preset voltage value as a sample gate input signal, generate a first control signal according to the sample gate input signal, and output the first control signal; a delay determination sub-circuit configured to receive the first control signal, delay the first control signal for a first preset time, determine whether a voltage value of the first control signal after delay is less than a voltage value of the first control signal before the delay, and if not, output a counting signal; and a counting control sub-circuit configured to receive the counting signal, perform counting according to the counting signal, and if a counted number reaches a preset number, output a second control signal.

A gate driver circuit, a display device and a driving method. The gate driver circuit includes: a scan signal generation circuit, wherein the scan signal generation circuit includes N1 stages of first output terminals, and the scan signal generation circuit is configured to output N1 first pulse scan signals stage by stage respectively through the N1 stages of first output terminals; and N2 level conversion circuits, wherein the N2 level conversion circuits are configured to output under a control of a plurality of conversion control signals N1 second pulse scan signals which are in one-to-one correspondence with the N1 first pulse scan signals, and the plurality of conversion control signals include a plurality of first sub-control signals which are the N1 first pulse scan signals, wherein N1 is an integer greater than or equal to 2, and N2 is an integer greater than or equal to 2.

A display drive circuit, a drive method thereof, and a display device are disclosed. The display drive circuit includes: a pixel circuit and a compensation circuit, the pixel circuit includes: a drive transistor, a light emitting device, a storage capacitor, and includes: a gating sub-circuit configured to control connection and disconnection between the control electrode of the drive transistor and a control terminal of the compensation circuit and connection and disconnection between a second electrode of the light emitting device and a sensing terminal of the compensation circuit in response to a signal of a scanning line; the compensation circuit includes: a voltage generating sub-circuit configured to generate a sensing voltage according to the drive current and a target data voltage, and a voltage adjusting sub-circuit configured to adjust a voltage of the control terminal according to the sensing voltage and a voltage of a second power supply terminal.