G09G2310/0297

Display substrate and display apparatus

A display substrate and a display apparatus are disclosed. The display substrate includes a display region and a peripheral region, the peripheral region includes a circuit region, and the display region includes a plurality of sub-pixels, a plurality of data lines extending along a first direction and a plurality of gate lines extending along a second direction crossing the first direction. The circuit region includes a plurality of driving unit groups. The circuit region includes a first sub-region and a second sub-region that are opposite to each other at two sides of the display region along the first direction, the first sub-region includes a plurality of multiplexing unit groups and the second sub-region includes a plurality of test unit groups.

DISPLAY DEVICE
20230005434 · 2023-01-05 ·

A display device may include a first pixel coupled to an emission control line, and an emission control stage for selectively coupling the emission control line to a first or second supply voltage line. The emission control stage may include: a first emission control transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the emission control line, and a main gate electrode coupled to a first node; a second emission control transistor including a first electrode coupled to the emission control line, a second electrode coupled to the second supply voltage line, and a main gate electrode coupled to a second node; and a third emission control transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the first node, a main gate electrode coupled to the second node, and a sub-gate electrode.

ELECTRO-OPTICAL APPARATUS, ELECTRONIC EQUIPMENT, AND DRIVING METHOD
20230005421 · 2023-01-05 ·

An electro-optical apparatus includes selector switches. One selector switch is provided for each data line. One data line is disposed for each pixel column of a pixel section that includes pixel circuits that are arranged in a matrix form. Each of the pixel circuits includes a drive transistor and a light-emitting element that emits light at luminance that is commensurate with a magnitude of a current supplied via the drive transistor. The selector switches write an input data signal to the data lines. The selector switches write a correction potential for correcting a threshold voltage of the drive transistor to the data lines that are divided into groups, at a timing different for each group.

Liquid crystal display device

The present invention has a pixel which includes a first switch, a second switch, a third switch, a first resistor, a second resistor, a first liquid crystal element, and a second liquid crystal element. A pixel electrode of the first liquid crystal element is electrically connected to a signal line through the first switch. The pixel electrode of the first liquid crystal element is electrically connected to a pixel electrode of the second liquid crystal element through the second switch and the first resistor. The pixel electrode of the second liquid crystal element is electrically connected to a Cs line through the third switch and the second resistor. A common electrode of the first liquid crystal element is electrically connected to a common electrode of the second liquid crystal element.

Driving method of a display panel, display driving device and electronic apparatus

Provided are a driving method for a display panel, display driving device and electronic apparatus. The display panel includes a shift register. A drive signal of the shift register includes a trigger signal and a clock signal. The driving method includes: a current FPS in a current display mode is acquired; a current trigger signal and a current clock signal of the shift register is determined according to the current FPS; the shift register is provided with the current trigger signal and the current clock signal. A refresh frequency of the current trigger signal is the same as the current FPS. The current clock signal is the same as a reference clock signal in a reference display mode at least within an effective action duration of the current trigger signal. The current FPS is less than or equal to the reference FPS in the reference display mode.

Drive control method and apparatus, and display device

Disclosed are a drive control method and apparatus and a display device. The drive control method may be applied to a controller, and include: adding at least one configuration instruction into a target region of one row of data to obtain a target row of data, wherein the configuration instruction is intended for self-configuration of a drive parameter by a first driver chip, and the target region includes at least one of a blank region and a region where display data is located; and sending the target row of data to the first driver chip.

Display device

A display device includes a display area of various shapes, has a reduced dead space, and displays an image. Further, the display device includes a display unit including a rounded corner portion, a first driving voltage supply line arranged in a first direction in a non-display area on one side of the display unit, a plurality of first driving voltage lines which supplies a driving voltage to a plurality of pixels and is arranged in a second direction that intersects with the first direction and being connected to the first driving voltage supply line, and a plurality of second driving voltage lines disconnected from the first driving voltage supply line.

Display device and driving method of the same

A display device includes: a data driver for supplying a data signal to output lines; a demultiplexer connected to each of the output lines, the demultiplexer to supply the data signal supplied to each output line to a first data line and a second data line; first pixels disposed in a (2j−1)-th column and a (2k−1)-th row, the first pixels being connected to the first data line, wherein j and k are positive integers; second pixels disposed in the (2j−1)-th column and a (2k)-th row, the second pixels being connected to the second data line; third pixels disposed in a (2j)-th column and the (2k−1)-th row, the third pixels being connected to the first data line; and fourth pixels disposed in the (2j)-th column and the (2k)-th row, the fourth pixels being connected to the second data line.

Active matrix substrate and method for manufacturing same

An active matrix substrate includes a first TFT and a second TFT, in which the first TFT includes a first oxide semiconductor layer and a first gate electrode arranged on a part of the first oxide semiconductor layer with a first gate insulating layer interposed therebetween, the first gate insulating layer has a layered structure including a first insulating film and a second insulating film arranged on the first insulating film, the second TFT includes a second oxide semiconductor layer having a higher mobility than the first oxide semiconductor layer and a second gate electrode arranged on a part of the second oxide semiconductor layer with a second gate insulating layer interposed therebetween, and the second gate insulating layer includes the second insulating film and does not include the first insulating film, and the second TFT further includes a lower insulating layer including the first insulating film arranged between the second oxide semiconductor layer and a substrate.

Multi-row buffering for active-matrix cluster displays

An active-matrix display with passive-matrix pixel clusters includes pixel clusters each having a cluster controller and a display controller operable to provide pixel data to the cluster controllers. Each pixel cluster includes pixels disposed in an array of N rows (N>=2) and M columns (M>=1), (N+1) memory banks, and a cluster controller operable to control the pixels and memory banks. Each memory bank is operable to store pixel data for a row of pixels. The cluster controller is operable to input pixel data for a row of pixels and store the pixel data in an input memory bank of the (N+1) memory banks and output stored pixel data from one or more output memory banks of the (N+1) memory banks that are not the input memory bank to control corresponding one or more rows of pixels.