An inverter circuit, a gate driver using the same, and a display device according to an embodiment are discussed. The inverter circuit can include a first transistor connected between a high potential voltage line and a first node; a second transistor having a gate connected to the first node and turned on according to a voltage of the first node to charge a second control node to a high potential voltage of the high potential voltage line; a third transistor having a gate connected to a first control node, a first electrode connected to the first node, and a second electrode connected to the second control node; and a fourth transistor having a gate connected to the first control node, a first electrode connected to the second control node, and a second electrode connected to a low potential voltage line.

A pixel circuit of a display device includes a driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node, and configured to supply an electric current to a light-emitting element; a first switch element configured to be turned on according to a gate-on voltage and supply a data voltage to the second node; a first capacitor connected between the second node and the third node; a second capacitor connected between the third node and the fourth node; and a third capacitor connected between the fourth node and the first node, or between the fourth node and a power line to which the pixel driving voltage is applied.

Embodiments of the disclosure relate to a display device and a data driving circuit. The display device comprises a display panel including a plurality of subpixels and a plurality of data lines electrically connected with the plurality of subpixels and a data driving circuit outputting a data voltage to the plurality of data lines, wherein the data driving circuit outputs the data voltage for image display to the plurality of data lines during an active period and outputs a step voltage to stepwise decrease a level of the data voltage to a preset target voltage level or stepwise increase the level of the data voltage from the target voltage level during a blank period different from the active period. Specifically, there may be provided a display device and a data driving circuit capable of enhancing display quality in a dark mura area and a bright mura area by outputting a step voltage to stepwise decrease the level of a data voltage to a preset target voltage level or stepwise increase the level of the data voltage from the target voltage level during a blank period.

A display device can include a display panel having a plurality of pixels disposed on a substrate, and a power supplier configured to supply a driving voltage to the display panel. The power supplier can include a first converter configured to receive an input voltage supplied from an external system and convert the input voltage into a boost voltage, a second converter configured to convert the boost voltage into the driving voltage, a first feedback unit configured to output a first pulse width modulation (PWM) signal to the first converter so that the boost voltage is proportional to a first reference voltage, and a second feedback unit configured to output a second PWM signal to the second converter so that the driving voltage is proportional to a second reference voltage.

First to fourth switches are provided so that conduction states are able to be controlled independently of each other. The first switch, the third switch, and the second switch are electrically connected in series between a first wiring and a third wiring. The fourth switch has a function of controlling a conduction state between the light-emitting element and a fourth wiring. In a first transistor, a gate is electrically connected to a node to which the third switch and the second switch are electrically connected, one of a source and a drain is electrically connected to a second wiring, and the other is electrically connected to the light-emitting element. A capacitor includes first and second electrodes, the first electrode is electrically connected to a node to which the first switch and the third switch are electrically connected, and the second electrode is electrically connected to the light-emitting element.

A driving circuit and a display panel are provided. The driving circuit includes a pixel circuit and a demultiplexing circuit. The pixel circuit includes a driving transistor, a light-emitting device, and a data writing module. The driving transistor is connected between a first power signal terminal and the light-emitting device in series, to generate a driving current. The data writing module is connected between the driving transistor and the demultiplexing circuit in series, to provide a data signal to the driving transistor. An output terminal of the demultiplexing circuit is connected to an input terminal of the data writing module through a data line. The demultiplexing circuit is configured to write the data signal to the data line when the driving transistor is performing threshold compensation.

A display panel and a display device are provided. The display panel includes a first display area and a second display area; and the second display area includes a transmission area. The sum of the resistivities of a first reset signal line, a first initialization signal line and a first bias adjustment signal line located in the first display area may not be greater than the sum of the resistivities of the second reset signal line, the second initialization signal line and the second bias adjustment signal line located in the second display area such that at least one of the first reset signal line, the first initialization signal line and the first these signal lines with relatively high resistivity requirements is disposed arranged on the film layer with a low signal lines resistivity of the signal line.

A display device includes a timing controller, a data driver controlled by the timing controller, and a display panel configured to display an image by the data driver. When a data signal is applied in an abnormal state, the data driver generates a voltage for display of black by itself, and supplies the voltage to the display panel.

The present disclosure discloses a display driving circuit. The display driving circuit is configured to have a function of detecting a short of a data line occurring on a display panel.

An embodiment provides a latch circuit which outputs, to a digital analog converter (DAC), a digital signal including grayscale data, the latch circuit including a first latch configured to store the digital signal and a second latch configured to output the digital signal by controlling first timing at which a level of a first signal included in the digital signal becomes an enable level, based on a center grayscale. The grayscale data includes first grayscale data and second grayscale data.