A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

A display panel has a display area including a plurality of pixel areas arranged in an array and a plurality of gate driving circuit areas. Each pixel area includes a pixel light-emitting sub-area and a pixel circuit sub-area arranged in a first direction. Pixel areas in each row correspond to at least two gate driving circuit areas each located between two adjacent pixel areas in this row. The display panel includes a gate driving circuit and a plurality of light-shielding portions. The gate driving circuit includes a plurality of shift registers that are cascaded. Each shift register includes a plurality of transistor groups, and each transistor group includes at least one transistor. Each light-shielding portion is located in a gate driving circuit area in which a transistor group is disposed, and is disposed on a periphery of the transistor group, and is electrically connected to a power supply signal line.

A variety of methods for driving electro-optic displays so as to reduce visible artifacts are described. Such methods include (a) applying a first drive scheme to a non-zero minor proportion of the pixels of the display and a second drive scheme to the remaining pixels, the pixels using the first drive scheme being changed at each transition; (b) using two different drive schemes on different groups of pixels so that pixels in differing groups undergoing the same transition will not experience the same waveform; (c) applying either a balanced pulse pair or a top-off pulse to a pixel undergoing a white-to-white transition and lying adjacent a pixel undergoing a visible transition; (d) driving extra pixels where the boundary between a driven and undriven area would otherwise fall along a straight line; and (e) driving a display with both DC balanced and DC imbalanced drive schemes, maintaining an impulse bank value for the DC imbalance and modifying transitions to reduce the impulse bank value.

The present application discloses a cross voltage compensation method for a display panel, a display panel and a display device. The cross voltage compensation method includes steps of transmitting a preset voltage signal to in-plane data lines after scan of scanning lines of a last row of a current frame is completed and before scanning lines of a first row of a next frame are started, keeping all the scanning lines at a close state while transmitting the preset voltage signal to in-plane data lines, and keeping all the scanning lines at a close state after scan of scanning lines of a last row of a current frame is completed and before scanning lines of a first row of a next frame are started, that is, V-blank time.

A gate-on-array (GOA) circuit is provided, and the GOA circuit includes a plurality of rows of cascading GOA units, at least four clock signal lines, and a first start trigger signal line. The plurality of rows of GOA units are divided into odd-row GOA units and even-row GOA units, and a first GOA unit of the odd-row GOA units is connected to the first start trigger signal line.

A display device, includes: a scan driver configured to sequentially supply scan signals having a turn-on level to the first scan line and the second scan line during a first period and to concurrently supply scan signals having a turn-on level to the first scan line and the second scan line during a second period after the first period, wherein: a mask period corresponds to a difference between a start point of the second period and a start point of the first period in a next frame period, a first frame period and a second frame period have different mask periods, a third frame period between the first frame period and the second frame period has a same mask period as the first frame period, and a fourth frame period between the first frame period and the second frame period has a same mask period as the second frame period.

A display device including a pixel comprises an EVDD driving unit outputting an AC driving voltage swinging between a high potential voltage and a low potential voltage according to voltages of a first control node and a second control node, and a plurality of sub-pixels connected to a data line and a gate line to receive the AC driving voltage by sharing an output node of the EVDD driving unit. Each of the sub-pixels may include a light emitting element, a driving element for supplying a current to the light emitting element according to a gate-source voltage, a switch element turned-on according to a scan signal to connect the data line to the gate of the driving element, and a capacitor connected between a gate and a source of the driving element.

Provided are a pixel driving circuit, a driving method and a display panel. The pixel driving circuit includes a driving transistor, a storage sub-circuit, a data writing sub-circuit, an initialization sub-circuit, a first light-emission control sub-circuit, a second light-emission control sub-circuit and a light-emitting element. The data writing sub-circuit is configured to write a data signal to a first electrode of the driving transistor in response to a second scan signal. The storage sub-circuit is configured to store the data signal written by the data writing sub-circuit. The initialization sub-circuit is configured to apply a reset voltage of an initial voltage terminal to the light-emitting element in response to a first scan signal. The first light-emission control sub-circuit is configured to apply a voltage of a first power terminal to the first electrode of the driving transistor in response to a first light-emission signal.

A display panel includes a distributor to transfer a second data signal to a second data line in a first period of a data period and to transfer a first data signal to a first data line in a second period of the data period, the second period being different from the first period; a first pixel electrically connected to the first data line, to initialize a first previous data signal in the data period in response to a first control signal, and to store the first data signal in the second period in response a scan signal; and a second pixel electrically connected to the second data line and to store the second data signal in the first period in response to the scan signal.

A method of driving an electro-optic display including a layer of electro-optic material disposed between a common electrode and a backplane including an array of pixel electrodes, each coupled to a transistor including a source, gate, and drain electrode. The gate electrode is coupled to a gate line, the source electrode is coupled to a scan line, and the drain electrode is coupled to the pixel electrode. A controller provides time-dependent voltages to the gate, scan, and common electrodes, including a common electrode that is the maximum voltage the controller is capable of applying, and a scan line voltage to every pixel that is the maximum voltage the controller is capable of applying. A gate voltage sufficient to activate the pixel transistor to the gate of every pixel transistor is applied, thereby applying voltage potential across the electro-optic material.