Methods for driving electro-optic displays, especially bistable displays, include (a) using two-part waveforms, the first part of which is dependent only upon the initial state of the relevant pixel; (b) measuring the response of each individual pixel and storing for each pixel data indicating which of a set of standard drive schemes are to be used for that pixel; (c) for at least one transition in a drive scheme, applying multiple different waveforms to pixels on a random basis; and (d) when updating a limited area of the display, driving “extra” pixels in an edge elimination region to avoid edge effects.

Precharge thinning drive is performed without causing rotation noise and without requiring complicated control. A signal generation circuit that supplies an image signal with a magnitude in accordance with a tone to be displayed to pixels via data lines in a tone display period and supplies a precharge voltage to the data lines in a precharge period before the tone display period in one horizontal scanning period, a signal distribution circuit that is provided between the signal generation circuit and the data lines and selects the data lines, and a control circuit that controls the signal distribution circuit such that a predetermined number of data lines are alternately not selected in the precharge period are provided, and the control circuit controls the signal distribution circuit such that non-selection of the data line is different every predetermined horizontal scanning period.

The present invention discloses an external compensation GOA circuit and a display panel. By adding a random detection signal output branch, a first output waveform of a scan signal line fulfilling normal driving is outputted in a normal time, and a second output waveform of the scan signal line fulfilling blanking time random detection is outputted in a blanking time, such that randomly detecting a threshold voltage of the drive transistor by using the blanking time of the scan signal can be achieved to further achieve external real time compensation of the threshold voltage shift, enhance uniformity of screen image display, and improve a lifespan of the display panel.

Methods for driving electro-optic displays, especially bistable displays, include (a) using two-part waveforms, the first part of which is dependent only upon the initial state of the relevant pixel; (b) measuring the response of each individual pixel and storing for each pixel data indicating which of a set of standard drive schemes are to be used for that pixel; (c) for at least one transition in a drive scheme, applying multiple different waveforms to pixels on a random basis; and (d) when updating a limited area of the display, driving “extra” pixels in an edge elimination region to avoid edge effects.

A variety of methods for driving electro-optic displays so as to reduce visible artifacts are described. Such methods include (a) applying a first drive scheme to a non-zero minor proportion of the pixels of the display and a second drive scheme to the remaining pixels, the pixels using the first drive scheme being changed at each transition; (b) using two different drive schemes on different groups of pixels so that pixels in differing groups undergoing the same transition will not experience the same waveform; (c) applying either a balanced pulse pair or a top-off pulse to a pixel undergoing a white-to-white transition and lying adjacent a pixel undergoing a visible transition; (d) driving extra pixels where the boundary between a driven and undriven area would otherwise fall along a straight line; and (e) driving a display with both DC balanced and DC imbalanced drive schemes, maintaining an impulse bank value for the DC imbalance and modifying transitions to reduce the impulse bank value.

A shift register, a gate driving circuit and a driving method for the same, and a liquid crystal display. The shift register includes: a pull-up sub-circuit configured to set a potential at a pull-up node to an operating potential when a first input signal is received via a first input terminal; a first output sub-circuit configured to output a gate driving signal at an output terminal according to a first clock signal received via a first clock signal terminal when the potential at the pull-up node is the operating potential; and a second output sub-circuit configured to output a gate driving signal at the output terminal when a second input signal is received via a second input terminal during a period other than a duration in which one frame of picture is displayed.

Provided is a display panel. The display panel includes multiple scanning lines, a gate driver circuit, and a timing controller. The timing controller is configured to: receive multiple data enable signals, generate a gate control signal, and provide the gate control signal for the gate driver circuit. The gate control signal includes a start signal, a first clock signal and a second clock signal. The multiple data enable signals are only within the active cycle. The timing controller is configured to generate a rising edge of the start signal within the vertical blanking cycle of the (N−1).sup.th frame cycle. Alternatively, the timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval formed by a rising edge and a falling edge of a first data enable signal in the N.sup.th frame cycle.

A display device includes: a plurality of pixel blocks each including a plurality of pixels; a scan driver supplying a scan signal to the scan lines and to supply a control signal to the control lines; a data driver supplying an image data voltage or a low grayscale data voltage to the data lines; and a power supply supplying a reference voltage to the pixels, wherein the pixels are configured to receive the image data voltage during a first scan period of a frame, and to receive the low grayscale data voltage during a second scan period of the frame, and the reference voltage supplied to a first pixel row of at least one of the pixel blocks in the first scan period is different from the reference voltage supplied to a last pixel row of at least one of the pixel blocks in the first scan period.

A display device includes pixels which are connected to first scan lines, second scan lines, third scan lines, emission control lines, and data lines; a scan driver which supplies a bias scan signal to each of the third scan lines at a first frequency and supplies a scan signal to each of the first scan line and the second scan line at a second frequency which corresponds to an image refresh rate of each of the pixels; an emission driver which supplies an emission control signal to each of the emission control lines at the first frequency; a data driver which supplies a data signal to each of the data lines at the second frequency; and a timing controller which controls driving of the scan driver, the emission driver, and the data driver.

Provided are a pixel driving circuit, a driving method and a display panel. The pixel driving circuit includes a driving transistor, a storage sub-circuit, a data writing sub-circuit, an initialization sub-circuit, a first light-emission control sub-circuit, a second light-emission control sub-circuit and a light-emitting element. The data writing sub-circuit is configured to write a data signal to a first electrode of the driving transistor in response to a second scan signal. The storage sub-circuit is configured to store the data signal written by the data writing sub-circuit. The initialization sub-circuit is configured to apply a reset voltage of an initial voltage terminal to the light-emitting element in response to a first scan signal. The first light-emission control sub-circuit is configured to apply a voltage of a first power terminal to the first electrode of the driving transistor in response to a first light-emission signal.