A variety of methods for driving electro-optic displays so as to reduce visible artifacts are described. Such methods include (a) applying a first drive scheme to a non-zero minor proportion of the pixels of the display and a second drive scheme to the remaining pixels, the pixels using the first drive scheme being changed at each transition; (b) using two different drive schemes on different groups of pixels so that pixels in differing groups undergoing the same transition will not experience the same waveform; (c) applying either a balanced pulse pair or a top-off pulse to a pixel undergoing a white-to-white transition and lying adjacent a pixel undergoing a visible transition; (d) driving extra pixels where the boundary between a driven and undriven area would otherwise fall along a straight line; and (e) driving a display with both DC balanced and DC imbalanced drive schemes, maintaining an impulse bank value for the DC imbalance and modifying transitions to reduce the impulse bank value.

A light emitting display device includes: a first switch connected between a data line and a first node and including a gate connected to a first scan line; a second switch connected between a first driving power line and a second node and including a gate electrode connected to the first node; a first capacitor connected between the first node and the second node; a light emitting element connected between the second node and a second driving power line; a scan driver applying a first A-scan signal and a first B-scan signal during different times to the first scan line; a data driver applying a first initialization signal and a data signal to the data line at different times; and a power supply portion applying a first driving voltage, a second driving voltage, and a third driving voltage to the first driving power line at different times.

The present application discloses a cross voltage compensation method for a display panel, a display panel and a display device. The cross voltage compensation method includes steps of transmitting a preset voltage signal to in-plane data lines after scan of scanning lines of a last row of a current frame is completed and before scanning lines of a first row of a next frame are started, keeping all the scanning lines at a close state while transmitting the preset voltage signal to in-plane data lines, and keeping all the scanning lines at a close state after scan of scanning lines of a last row of a current frame is completed and before scanning lines of a first row of a next frame are started, that is, V-blank time.

A method for driving electro-optic displays including electro-optic material disposed between a common electrode and a backplane. The backplane includes an array of pixel electrodes, each coupled to a transistor. A display controller applies waveforms to the pixel electrodes. The method includes applying first measurement waveforms to a first portion of the pixel electrodes. During each frame of the first measurement waveforms, the same time-dependent voltages are applied to each pixel electrode of the first portion of pixel electrodes. The method includes determining the impedance of the electro-optic material in proximity to the first portion of pixel electrodes based on a measurement of the current flowing through a current measurement circuit and the time-dependent voltages applied to each pixel electrode during the first measurement waveforms, and selecting driving waveforms based on the impedance of the electro-optic material in proximity to the first portion of pixel electrodes.

A display may have an array of pixels to display images. Gate line driver circuitry may have stages that supply gate line signals. A gate line may be located in each row of the pixels. Each stage may have an output block that produces a respective one of the gate line signals and may have a carry block that separately produces a carry signal that is provided to a later stage in the gate line driver circuitry. A memory may be provided in at least some of the stages to store signals produced by the output blocks during intraframe pausing operations. At the end of an intraframe pause, the stored signals may be used in restarting production of the gate line signals by output blocks in the gate line driver stages. Circuitry may be used to separately reset the output block and suppress carry signal production by the carry block.

A display apparatus includes a display panel and a driving circuit. The display panel includes pixels. Each of the pixels is connected to one of gate lines and one of data lines. The driving circuit drives the gate lines and the data lines to display an image on the display panel. The driving circuit alternately provides a first polarity data driving signal and a second polarity data driving signal to each of the plurality of data lines. During an asymmetrical mode, the first polarity data driving signal is provided to first data lines of the data lines during a first frame period before a blank period begins, and the second polarity data driving signal is provided to the first data lines during a second frame period after the blank period ends. The second frame period excludes the blank period.

A method of driving an electro-optic display including a layer of electro-optic material disposed between a common electrode and a backplane including an array of pixel electrodes, each coupled to a transistor including a source, gate, and drain electrode. The gate electrode is coupled to a gate line, the source electrode is coupled to a scan line, and the drain electrode is coupled to the pixel electrode. A controller provides time-dependent voltages to the gate, scan, and common electrodes, including a common electrode that is the maximum voltage the controller is capable of applying, and a scan line voltage to every pixel that is the maximum voltage the controller is capable of applying. A gate voltage sufficient to activate the pixel transistor to the gate of every pixel transistor is applied, thereby applying voltage potential across the electro-optic material.

A variety of methods for driving electro-optic displays so as to reduce visible artifacts are described. Such methods includes updating a display having a plurality of display pixels with a first image, identifying display pixels with edge artifacts after the first image update, and storing the identified display pixels information in a memory. In particular, the methods are effective for minimizing edge ghosting when a pixel of an active matrix electrophoretic display undergoes a white to white transition or a black to black transition during an update between first and second images.

A display device can include a display panel, in which a subpixel including a transistor where data lines and gate lines intersect, is disposed; a gate driving unit that sequentially outputs a gate signal to the gate lines; a data driving unit that outputs a data voltage to the data lines according to the gate signal provided to each gate line, and outputs to the data lines during a blank time before a specific frame, data voltages having an output waveform that is identical to data voltages of at least one gate line of the specific frame; and a timing controller that controls the gate driving unit and the data driving unit, and performs a pixel compensation which changes data provided to each subpixel.

A display device comprises: a display panel including a first display area comprising a first pixels, and a second display area comprising a second pixels, each pixel including a light emitting element; a data driver circuit configured to output data voltages of an image to the first and second pixels; a gate driver configured to output scan signals to the first and second pixels; and a power supply configured to generate a low-potential power supply voltage that is applied to the light emitting element included in each pixel, the low-potential power supply voltage switching between a first level such that the light emitting element is capable of emitting light, and a second level such that the light emitting element cannot emit light, wherein a frame period of the display device includes an addressing period during which the low-potential power supply voltage switches from the second level to the first level.