Pixel circuit, display panel and display device are provided. The pixel circuit includes a driving module, a data writing module, a first reset module, a threshold compensation module, light emitting control modules, a leakage suppression module, a storage capacitor, a first capacitor, and a light emitting module. A first terminal of the first reset module is electrically connected to a reference signal terminal. A first terminal of the threshold compensation module is electrically connected to a second terminal of the driving module. A control terminal of the driving module is electrically connected to a first node. A second terminal of the first reset module and a second terminal of the threshold compensation module are both electrically connected to the first node through the leakage suppression module. A connection node between the leakage suppression module and the second terminal of the first reset module is a second node.

Provided are an array substrate and a fabrication method therefor, a shift register unit, and a display panel. The array substrate includes a first transistor having a double gate structure, and further includes an active layer arranged on one side of the base substrate and a first conductive layer. The active layer includes a first conductor portion connected between a first semiconductor portion and a second semiconductor portion, the first semiconductor portion and a second semiconductor portion forming a channel region of the first transistor. The first conductive layer includes a first conductive portion connected to a stable voltage source, an orthographic projection of the first conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first conductor portion on the base substrate, and the first conducting portion and the first conductor portion form two electrodes of a parallel-plate capacitor.

A scan driver includes a plurality of stages. A n-th stage among the plurality of stages includes a first input unit controlling a voltage of a first node in response to a previous carry signal, a scan output unit outputting a current scan signal corresponding to a scan clock signal in response to the voltage of the first node, a first switching unit controlling a voltage of a second node in response to the previous carry signal, a sensing output unit outputting a current sensing signal corresponding to a sensing clock signal in response to the voltage of the second node, a carry output unit outputting a current carry signal corresponding to a carry clock signal in response to the voltage of the second node, and a second switching unit controlling the voltage of the second node in response to the sensing clock signal or the carry clock signal.

Gate Driver on Array (GOA) circuit and display device solving problem of electrical stress easily biasing threshold voltage of thin film transistor (TFT), are provided. The GOA circuit including m cascaded GOA units, wherein an n.sup.th GOA unit includes a pull-up control unit, a pull-up unit, a compensation control unit, and a pull-down unit.

A display device includes: a (k−1)-th scan line and a k-th scan line which are parallel to each other; a j-th data line which crosses the (k−1)-th scan line and the k-th scan line; and a subpixel connected to the (k−1)-th scan line, the k-th scan line, and the j-th data line, wherein the subpixel includes: a driving transistor configured to control a driving current flowing from a first electrode thereof to a second electrode thereof according to a data voltage applied to a first gate electrode thereof, the driving transistor having a second gate electrode connected to the (k−1)-th scan line; and a light emitting element configured to emit light according to the driving current.

A pixel circuit, a method of driving the same, and a display device are provided. An input end of an anode reset transistor is connected to an output end of a driving transistor, and an output end of the anode reset transistor is connected to an anode of an organic light emitting diode to collect a leakage current from the anode of the organic light emitting diode through the anode reset transistor to the output end of the driving transistor in an light emitting state. Part of the collected current at the output end of the driving transistor enters the anode of the organic light emitting diode.

A display device includes a display panel including pixels coupled to a first scan line and a data line, a power supply to supply voltages, a scan driver to provide a first scan signal to the first scan line a plurality of times for a first frame period (FFP), a data driver to supply a data signal to the data line, and a timing controller to control driving of components. The FFP includes: a first active period (FAP), in which the data signal is supplied; and a first blank period (FBP), in which the data signal is not supplied. The power supply provides on-bias power having a first voltage level (FVL) in the FAP, and provides on-bias power having a second voltage level (SVL) in the FBP. The FBP following the FAP includes a first dimming period in which the on-bias power gradually changes from the FVL to the SVL.

The light emitting display panel includes a plurality of pixels, a plurality of gate lines transferring gate signals to the plurality of pixels, a plurality of data lines transferring data voltages to the plurality of pixels, and a sensing line connected to a plurality of light emitting devices respectively included in the plurality of pixels. Each of the plurality of pixels includes a light emitting device, a sensing control transistor including a first terminal connected to a first terminal of the light emitting device and a gate connected to a sensing control line, and a sensing switching transistor including a first terminal connected to a second terminal of the sensing control transistor, a second terminal connected to the sensing line, and a gate connected to a sensing switching line.

A gate driving unit, a gate driving circuit, a gate driving method, and a display device are provided. The gate driving unit includes a first output circuit and a second output circuit; the second output circuit comprises a first output sub-circuit; the first output circuit is respectively electrically connected to the first node, the second node and the first gate driving signal output end and is configured to control the first gate driving signal output end to output a first gate driving signal under the control of the potential of the first node and the potential of the second node; the first output sub-circuit is respectively electrically connected to the first node, the second gate driving signal output end and the first clock signal end, and is configured to control the second gate driving signal output end to be connected to the first clock signal end.

Disclosed are a gate driver circuit having a reduced size, and a display device including the same. The gate driver circuit includes a plurality of stage circuits. Each stage circuit supplies a gate signal to each of gate lines arranged in a display panel, and includes a M node, a Q node, a QH node, and a QB node. Each stage circuit includes a gate signal output module configured to operate based on a voltage level of the Q node or a voltage level of the QB node to output first to j-th gate signals based on first to j-th scan clock signals or a first low-potential voltage.