A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, and the driving module includes a driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, and the non-light-emitting stage includes a bias adjustment stage, in which one of a source and a drain of the driving transistor receives a bias adjustment signal. An operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2, where L1>L2. A working process of the display panel in the first mode includes a first frame, and a working process of the display panel in the second mode includes a second frame.

A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations.

In a display panel, pixels each including a plurality of sub-pixels are arranged in a matrix form, wherein each of the plurality of sub-pixels includes: an inorganic light-emitting element; a constant current generator circuit that provides a driving current to the inorganic light-emitting element on the basis of a constant current generator data voltage; and a PWM circuit for controlling the time for the driving current to flow through the inorganic light-emitting element on the basis of a PWM data voltage, wherein the constant current generator circuit includes a first driving transistor and the PWM circuit includes a second driving transistor, and wherein the constant current generator circuit or the PWM circuit comprises an internal compensation circuit that compensates for electrical characteristics of the first driving transistor and the second driving transistor.

The present disclosure provides a display device and a driving circuit. In the display device, a first subpixel is connected to a first data line and a first reference voltage line, and includes an emitting device and a driving transistor; and a second subpixel is connected to a second data line and a second reference voltage line, and includes an emitting device and a driving transistor. The driving time of the first subpixel includes a first initialization time in which a reference voltage is applied to the first reference voltage line and a first tracking time in which a voltage of the first reference voltage line increases from the reference voltage and then is saturated. Sensing times for subpixels having different channel sizes are reduced.

A display device includes: a display area and a non-display area; a first pixel area and a second pixel area, each provided in the display area; scan lines extending in a first direction and disposed in the first pixel area and the second pixel area; first sub-scan lines extending in a second direction and disposed in the first pixel area, the second direction intersecting the first direction; second sub-scan lines extending in the second direction and disposed in the first pixel area and the second pixel area; and a pad part provided in the non-display area, the pad part being electrically connected to the first sub-scan lines and the second sub-scan lines. The scan lines are electrically connected to at least one of the first sub-scan lines and the second sub-scan lines. The first sub-scan lines do not overlap the second pixel area in a plan view.

A display device including a display area and a non-display area, an inorganic insulating layer disposed on a substrate, the inorganic insulating layer disposed in the display area and the non-display area, pixels disposed on the substrate and overlapping the inorganic insulating layer in a plan view, the pixels disposed in the display area, and an organic insulating layer disposed on the substrate and overlapping the inorganic insulating layer and the pixels in a plan view, the organic insulating layer disposed at least in the display area. The non-display area includes an organic layer-free area including at least one of a corner and an outer edge area of the display device. The organic insulating layer is disposed on a portion of the substrate so as to be disposed in an area except for the organic layer-free area.

A pixel of an OLED display device includes a capacitor coupled between first and second nodes, first and second transistors, each including a gate receiving a respective initialization signal, a first terminal receiving a first power supply voltage, and a second terminal coupled to the capacitor, a third transistor including a first terminal coupled to a data line and a second terminal coupled to the first node, a fourth transistor including a gate coupled to the second node, a first terminal receiving the first power supply voltage, and a second terminal coupled to a third node, a fifth transistor including a first terminal coupled to the third node and a second terminal coupled to the second node, sixth and seventh transistors receiving a scan signal, eighth and ninth transistors receiving an emission signal, and an OLED.

Display devices are disclosed. In one example, a display device includes light emitting element groups each including light emitting element units, each of the light emitting element units including first, second and third light emitting elements. Each of the light emitting element groups includes first drive circuits that drive the first light emitting elements, second drive circuits that drive the second light emitting elements, and third drive circuits that drive the third light emitting elements, and in each of the light emitting element groups, the number of first drive circuits is equal to the number of first light emitting elements, the number of second drive circuits is less than the number of second light emitting elements, and the number of third drive circuits is less than the number of third light emitting elements.

A pixel circuit and a display device including the same are disclosed. The pixel circuit of this disclosure includes a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and configured to supply an electric current to a light emitting element; a first switch element configured to be turned on according to a gate-on voltage of a scan pulse to supply a data voltage to the second node; and a second switch element configured to be turned off according to a gate-off voltage of a light emitting control pulse generated in antiphase of the scan pulse.

A pixel circuit and a display panel including the same are disclosed. The pixel circuit may include a driving element including a gate connected to a first node to which a data voltage is configured to be applied, a first electrode connected to a high-potential voltage line, and a second electrode connected to a second node; a first switch element connected between the second node and a third node; a second switch element connected between the second node and a fourth node; a third switch element connected between the fourth node and a reference voltage line; a first capacitor connected between the first node and the third node; and a second capacitor connected between the third node and the fourth node.