Patent classifications
G09G2340/0435
Scan driving circuit and display device including the same
A scan driving circuit of a display device includes a first output terminal electrically connected to a first scan line, a second output terminal electrically connected to a second scan line, a first masking circuit electrically connecting the first output terminal and the second output terminal and outputting, as a first scan signal, a second scan signal to the first output terminal, a driving circuit outputting the second scan signal to the second output terminal in response to clock signals and a carry signal, and a second masking circuit masking the second scan signal to a predetermined level in response to the second masking signal, wherein the first masking circuit electrically disconnects the first output terminal from the second output terminal in response to a first masking signal.
INVERTER CIRCUIT, GATE DRIVER USING THE SAME, AND DISPLAY DEVICE
An inverter circuit, a gate driver using the same, and a display device according to an embodiment are discussed. The inverter circuit can include a first transistor connected between a high potential voltage line and a first node; a second transistor having a gate connected to the first node and turned on according to a voltage of the first node to charge a second control node to a high potential voltage of the high potential voltage line; a third transistor having a gate connected to a first control node, a first electrode connected to the first node, and a second electrode connected to the second control node; and a fourth transistor having a gate connected to the first control node, a first electrode connected to the second control node, and a second electrode connected to a low potential voltage line.
Display apparatus
A display apparatus comprises a mirror assembly, a first mirror of the mirror assembly oscillating about a first axis upon excitation by a first excitation signal and the first or a second mirror of the mirror assembly oscillating about a second axis upon excitation by a second excitation signal, a light source projecting a light beam onto the mirror assembly for deflection by the mirror assembly towards an image area, the light source being controlled according to pixels of image frames, a gaze tracker detecting a user's region of interest, ROI, within the image area, and a controller modulating one of the excitation signals by a first modulation signal which is dependent on the ROI detected by the gaze tracker.
Electroluminescent display device
An electroluminescent display device includes a pixel configured to display an image based on a difference between a display data voltage and a first reference voltage, a driving voltage generation circuit configured to supply the display data voltage to the pixel through a data line, and a sensing circuit configured to supply the first reference voltage to the pixel through a sensing line. The sensing circuit includes a sensing channel terminal coupled to the sensing line, a switch coupled between the sensing channel terminal and an input terminal for the first reference voltage, and a sampling circuit configured to sense a voltage of the sensing line which has changed from the first reference voltage independent of driving characteristics of the pixel in a vertical blank period in which the switch is turned off.
Performing asynchronous memory clock changes on multi-display systems
Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.
Display device and data driving circuit
Embodiments of the disclosure relate to a display device and a data driving circuit. The display device comprises a display panel including a plurality of subpixels and a plurality of data lines electrically connected with the plurality of subpixels and a data driving circuit outputting a data voltage to the plurality of data lines, wherein the data driving circuit outputs the data voltage for image display to the plurality of data lines during an active period and outputs a step voltage to stepwise decrease a level of the data voltage to a preset target voltage level or stepwise increase the level of the data voltage from the target voltage level during a blank period different from the active period. Specifically, there may be provided a display device and a data driving circuit capable of enhancing display quality in a dark mura area and a bright mura area by outputting a step voltage to stepwise decrease the level of a data voltage to a preset target voltage level or stepwise increase the level of the data voltage from the target voltage level during a blank period.
Image Display Control Method and Apparatus, and Image Display Device
Disclosed are an image display control method and apparatus, and an image display device. The method includes: a refresh rate of a display screen is acquired; display time of a target image on a predetermined time axis is adjusted according to the refresh rate, so as to obtain adjusted display time, wherein the predetermined time axis is a refresh cycle of each frame of the target image when the display screen is at a target refresh rate; and according to the adjusted display time, the display screen is controlled to display the target image. According to the present disclosure, the technical problem of visual crosstalk when a Light Emitting Diode (LED) display screen displays a dynamic image is solved.
RECEIVER OF DISPLAY DRIVER AND OPERATING METHOD THEREOF
A receiver of a display driver and an operating method of the receiver of the display driver are provided. The receiver of the display driver includes an input interface, an operational amplifier and a bias current control circuit. The input interface receives image data. The operational amplifier is coupled to the input interface and includes a bias current circuit. The bias current control circuit adjusts a bias current of the bias current circuit according to a data rate of the image data. The operating method is adapted to the receiver of the display driver.
Method of driving display panel including compensating for flicker and display apparatus for performing the same
A method of driving a display panel includes dividing an input image into a plurality of segments, generating a flicker value of a segment of the plurality of segments, determining whether to compensate the flicker value of the segment or not according to a segment size, compensating the flicker value of the segment based on the segment size, determining a frame rate of the display panel based on the flicker value of the segment and outputting a data voltage to the display panel in the frame rate. The flicker value of the segment is compensated based on the flicker value of the segment and flicker values of segments that are adjacent to the segment.
Video pipeline system and method for improved color perception
A system is provided for facilitating an enhanced video pipeline in order to improve color perception. The system comprises a first source configured to generate a first video stream, a second source configured to generate a second video stream, and a computing device. In this context, the computing device is configured to superpose the first video stream onto the second video stream, thereby generating an output video stream. The computing device is further configured to calculate weighting factors for individual pixels or discrete pixel sets of adjacent individual pixels of the output video stream by analyzing the first video stream and/or the second video stream.