A signal conversion device includes a first converting section configured to convert a clock signal input through a first signal line, a data signal input through a second signal line, and a control signal input through a third signal line, into pulse signals including a first pulse train and a second pulse train; and a transmitting section configured to transmit the first pulse train through a fourth signal line and the second pulse train through a fifth signal line, wherein the control signal is a signal that, through a level transition, causes a control target device to switch between an active state and an inactive state, and wherein the first converting section is configured to put successive pulses into at least one of the first pulse train and the second pulse train in response to the level transition of the control signal.

An apparatus may include a first and second servo channels configured to output first and second position information to first and second writers, respectively, via a shared write path such that the first and second writers write first and second position information to first and second magnetic recording medium surfaces, respectively. In addition, the apparatus may include a controller configured to control the shared write path such that write access is changed between the first servo channel and second servo channel a plurality of times during a revolution of the first magnetic recording medium surface and second magnetic recording medium surface.

A sequence of symbols is generated to describe a set of write data, the symbols having a length of nT, where T is a channel clock rate and n is an integer over a predetermined range. Bi-directional write currents are applied to a write pole to record the sequence of symbols to a magnetic storage medium. The write pole has an effective footprint with a downtrack length of mT, where m is an integer. The write currents are switched between a first rail current and a second rail current for alternating symbols, the write currents further transitioning to an intermediate current value for at least one channel clock period for symbols longer than 1T. Write currents are applied to the write pole when recording symbols having a length longer than mT using the effective footprint of the write pole as an interval.

A data storage device is disclosed comprising a disk comprising servo data, and an actuator configured to actuate a head over the disk. A servo controller is configured to generate digital control values at a first sample rate based on the servo data and transmit the digital control values over a serial interface to a driver circuit. The driver circuit is configured to generate predictive oversampled control values at a second sample rate higher than the first sample rate based on at least two of the digital control values received from the servo controller, apply the predictive oversampled control values to a digital-to-analog converter (DAC) to generate an analog control signal, and apply the analog control signal to the actuator.

An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.

Systems and methods are disclosed for detecting and compensating for timing excursions in a data channel. If a signal contains discontinuities in phase, a detector of the channel may lose lock on the signal, resulting in the channel incorrectly adjusting a sampling phase toward a following symbol or previous symbol. This is referred to as a cycle slip, where the integer alignment of the sampling of a signal contains a discontinuity over the duration of a sector, preventing decoding of the signal. A circuit may be configured to detect a cycle slip during processing of a signal at a data channel based on timing error values, and when the signal fails to decode, shift an expected sampling phase of a detector for a subsequent signal processing attempt. Shifting the expected sampling phase can cause the channel to adjust the sampling phase in the correct direction, thereby preventing a cycle slip.

An apparatus may include a first and second servo channels configured to output first and second position information to first and second writers, respectively, via a shared write path such that the first and second writers write first and second position information to first and second magnetic recording medium surfaces, respectively. In addition, the apparatus may include a controller configured to control the shared write path such that write access is changed between the first servo channel and second servo channel a plurality of times during a revolution of the first magnetic recording medium surface and second magnetic recording medium surface.

An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock.

Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.

An apparatus may include a circuit configured to process an input signal using a set of channel parameters. The circuit may produce, using a first adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the input signal. The circuit may further approximate a second set of channel parameters of a second adaptation algorithm for use by the circuit as the set of channel parameters in processing the input signal based on the first set of channel parameters and a relationship between a third set of channel parameters generated using the first adaptation algorithm and a fourth set of channel parameters generated using the second adaptation algorithm. In addition, the circuit may perform the processing of the input signal using the second set of channel parameters as the set of channel parameters.