G11B20/10222

BI-LEVEL ADAPTIVE EQUALIZER
20210075650 · 2021-03-11 ·

At least some aspects of the present disclosure provide for a method. In at least one examples, the method includes applying first equalization to a received data signal to generate an equalizer signal and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result. The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages. The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts and applying second equalization to the received data signal based on the determined relationship among the plurality of counts.

Write current switching using an effective size of a media thermal spot produced by a heat-assisted magnetic storage device
10885932 · 2021-01-05 · ·

A heat-assisted magnetic recording device includes a write pole positionable adjacent a magnetic recording medium and configured to write data to the medium. A near-field transducer is situated proximate the write pole and configured to produce a thermal spot on the medium. A channel circuit is configured to generate a sequence of symbols having a length of nT, where T is a channel clock rate and n is an integer over a predetermined range. A write driver is configured to apply bi-directional write currents to the write pole to record the sequence of symbols at a location of the thermal spot on the medium, wherein a duration of applying the write currents to the write pole by the write driver is dependent on a length of the sequence of symbols and the effective thermal spot size.

ON HEAD MICROELECTRONICS FOR WRITE SYNCHRONIZATION

The presently disclosed technology teaches integrating disc drive electronics into a transducer head. Decreased electrical transit times and data processing times can be achieved by placing the electronics on or within the transducer head because electrical connections may be made physically shorter than in conventional systems. The electronics may include one or more of a control system circuit, a write driver, and/or a data buffer. The control system circuit generates a modified clock signal that has a fixed relation to phase and frequency of a bit-detected reference signal that corresponds to positions of patterned bits on the disc. The write driver writes outgoing data bits received from an external connection to off-head electronics directly to the writer synchronized with the modified clock signal. The data buffer stores and converts digital data bits sent from the off-head electronics to an analog signal that is synchronized with the modified clock signal.

Constant-Density Writing for Magnetic Storage Media
20200294549 · 2020-09-17 · ·

The present disclosure describes aspects of constant-density writing for magnetic storage media. In some aspects, a constant-density writer delays transitions between bits within write data to enable constant-density writing. The write data has an initial bit period based on a constant clock signal, which is generated based on the rotation of a media disk. The constant-density writer modifies the write data to generate phase-delayed write data, which has a bit period that is greater than or equal to the initial bit period. To realize this bit period, the constant-density writer changes write phases of bit transitions within the write data. The constant-density writer can also insert stretch bits, filter single-bit transitions, and mitigate glitches within the phase-delayed write data.

Multi-signal realignment for changing sampling clock

An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.

On head microelectronics for write synchronization

The presently disclosed technology teaches integrating disc drive electronics into a transducer head. Decreased electrical transit times and data processing times can be achieved by placing the electronics on or within the transducer head because electrical connections may be made physically shorter than in conventional systems. The electronics may include one or more of a control system circuit, a write driver, and/or a data buffer. The control system circuit generates a modified clock signal that has a fixed relation to phase and frequency of a bit-detected reference signal that corresponds to positions of patterned bits on the disc. The write driver writes outgoing data bits received from an external connection to off-head electronics directly to the writer synchronized with the modified clock signal. The data buffer stores and converts digital data bits sent from the off-head electronics to an analog signal that is synchronized with the modified clock signal.

Magnetic disk device and method for demodulating servo demodulation position

According to one embodiment, a magnetic disk device includes a disk including two first servo sectors arranged side by side in a circumferential direction and a second servo sector located between the two first servo sectors, a head that writes data to the disk and reads data from the disk, and a controller that adjusts a second timing at which the second servo sector is demodulated based on a first timing at which the first servo sector is demodulated, and corrects a first initial phase of a first demodulation signal obtained by demodulating the second servo sector at the second timing, based on a first amplitude of the first demodulation signal.

READBACK WAVEFORM OVERSAMPLING METHOD AND APPARATUS
20200251132 · 2020-08-06 ·

A read channel is configured to obtain an analog readback waveform from a magnetic recording medium of a disk drive at a sampling rate of one sample per one written bit. A buffer is coupled the read channel. Circuitry is configured to inject a plurality of different phase offsets into the read channel for each of a plurality of revolutions of the medium. The circuitry is also configured to store, in a buffer, an amplitude of the readback waveform for each of the different phase offsets. The circuitry is further configured to generate an oversampled readback waveform using the amplitudes stored in the buffer.

Timing index writes to a tape medium

Aspects of the present disclosure relate to a method for timing index write to a tape medium of a tape system. Index write timing data that specifies index write timing based on file metadata attributes is stored. Metadata attributes of a first file are analyzed to determine whether a first index should be written at a first time based on the index write timing data. In response to determining that an index should be written, the first index is written to the tape medium at the first time.

Approximated parameter adaptation

An apparatus can include a circuit configured to process an input signal using a set of channel parameters. The circuit can produce, using a first adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the input signal. The circuit can further approximate a second set of channel parameters of a second adaptation algorithm for use by the circuit as the set of channel parameters in processing the input signal based on the first set of channel parameters and a relationship between a third set of channel parameters generated using the first adaptation algorithm and a fourth set of channel parameters generated using the second adaptation algorithm. In addition, the circuit can perform the processing of the input signal using the second set of channel parameters as the set of channel parameters.