Patent classifications
G11B20/10222
Preamble defect detection and mitigation
Systems and methods are disclosed for detection and mitigation of defects within a preamble portion of a signal, such as a data sector preamble recorded to a data storage medium. In certain embodiments, an apparatus may comprise a circuit configured to synchronize a sampling phase for sampling a signal pattern. The circuit may sample a preamble field of the signal pattern to obtain sample values, split the sample values into a plurality of groups, determine defect groups having samples corresponding to defects in the preamble field, remove the defect groups from the plurality of groups, and synchronize the sampling phase based on the plurality of groups.
Parallelized writing of servo RRO/ZAP fields
An apparatus may include a first and second servo channels configured to output first and second position information to first and second writers, respectively, via a shared write path such that the first and second writers write first and second position information to first and second magnetic recording medium surfaces, respectively. In addition, the apparatus may include a controller configured to control the shared write path such that write access is changed between the first servo channel and second servo channel a plurality of times during a revolution of the first magnetic recording medium surface and second magnetic recording medium surface.
Timing index writes to a tape medium
Aspects of the present disclosure relate to a method for timing index write to a tape medium of a tape system. Index write timing data that specifies index write timing based on file metadata attributes is stored. Metadata attributes of a first file are analyzed to determine whether a first index should be written at a first time based on the index write timing data. In response to determining that an index should be written, the first index is written to the tape medium at the first time.
In-circuit calibration of anti-aliasing filter
A computer-implemented method according to one embodiment includes performing anti-aliasing filtering on each of a plurality of signals, each signal having a frequency that is a different fraction of a frequency of a data read clock. An amplitude of each of the signals is measured after the anti-aliasing filtering. In response to the amplitudes of the signals being within a predefined range, anti-aliasing settings used during the anti-aliasing filtering are stored. In response to the amplitudes of the signals being outside the predefined range, the anti-aliasing settings are changed. A computer program product according to another embodiment includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. The program instructions are executable by a processing circuit to cause the processing circuit to perform the foregoing method.
Chirped current profile with undershoot feature
Systems and methods for a providing a chirped current profile with an undershoot for a channel preamplifier are described. A method for writing bits in a magnetic recording disc may include applying an overshoot to a write current which is supplied to a magnetic writer of the magnetic recording disc and applying an undershoot to the write current after the overshoot is applied to at least partially de-saturate the magnetic writer. The method may also include writing a bit to the magnetic recording disc with the magnetic writer using the supplied write current. In some examples, the application of a short negative pulse after an overshoot portion of the write current waveform is delivered to the head during a write operation that writes the bit to the magnetic recording disc.
Write current switching in a data storage device using an effective footprint of a write pole
A sequence of symbols is generated to describe a set of write data, the symbols having a length of nT, where T is a channel clock rate and n is an integer over a predetermined range. Bi-directional write currents are applied to a write pole to record the sequence of symbols to a magnetic storage medium. The write pole has an effective footprint with a downtrack length of mT, where m is an integer. The write currents are switched between a first rail current and a second rail current for alternating symbols, the write currents further transitioning to an intermediate current value for at least one channel clock period for symbols longer than 1T. Write currents are applied to the write pole when recording symbols having a length longer than mT using the effective footprint of the write pole as an interval.
DETERMINING BIT ASPECT RATIOS FOR PARTIALLY-OVERLAPPING MAGNETIC RECORDING TRACKS
A method involves determining bit aspect ratios for interlaced tracks written to a magnetic recording medium. The interlaced tracks include top tracks that are written partially overlapping with bottom tracks. Isolated test tracks are written at first different bit aspect ratios to determine a top bit aspect ratio that achieves a first target areal density for the isolated test tracks. Test tracks are written at second different bit aspect ratios to determine a bottom bit aspect ratio that achieves a second target areal density for the test tracks. Top test tracks of the test tracks are written at the top bit aspect ratio. The top and bottom bit aspect ratios are selected to subsequently write partially-overlapping tracks on the magnetic recording medium.
Multi-signal realignment for changing sampling clock
An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.
Timing excursion recovery
Systems and methods are disclosed for detecting and compensating for timing excursions in a data channel. If a signal contains discontinuities in phase, a detector of the channel may lose lock on the signal, resulting in the channel incorrectly adjusting a sampling phase toward a following symbol or previous symbol. This is referred to as a cycle slip, where the integer alignment of the sampling of a signal contains a discontinuity over the duration of a sector, preventing decoding of the signal. A circuit may be configured to detect a cycle slip during processing of a signal at a data channel based on timing error values, and when the signal fails to decode, shift an expected sampling phase of a detector for a subsequent signal processing attempt. Shifting the expected sampling phase can cause the channel to adjust the sampling phase in the correct direction, thereby preventing a cycle slip.
PARALLELIZED WRITING OF SERVO RRO/ZAP FIELDS
An apparatus may include a first and second servo channels configured to output first and second position information to first and second writers, respectively, via a shared write path such that the first and second writers write first and second position information to first and second magnetic recording medium surfaces, respectively. In addition, the apparatus may include a controller configured to control the shared write path such that write access is changed between the first servo channel and second servo channel a plurality of times during a revolution of the first magnetic recording medium surface and second magnetic recording medium surface.