G11B20/10222

HYBRID TIMING RECOVERY
20180366155 · 2018-12-20 · ·

An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock.

SAMPLING FOR MULTI-READER MAGNETIC RECORDING
20180366156 · 2018-12-20 · ·

Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.

APPROXIMATED PARAMETER ADAPTATION

An apparatus may include a circuit configured to process an input signal using a set of channel parameters. The circuit may produce, using a first adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the input signal. The circuit may further approximate a second set of channel parameters of a second adaptation algorithm for use by the circuit as the set of channel parameters in processing the input signal based on the first set of channel parameters and a relationship between a third set of channel parameters generated using the first adaptation algorithm and a fourth set of channel parameters generated using the second adaptation algorithm. In addition, the circuit may perform the processing of the input signal using the second set of channel parameters as the set of channel parameters.

Sampling for multi-reader magnetic recording

Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.

ON HEAD MICROELECTRONICS FOR WRITE SYNCHRONIZATION

The presently disclosed technology teaches integrating disc drive electronics into a transducer head. Decreased electrical transit times and data processing times can be achieved by placing the electronics on or within the transducer head because electrical connections may be made physically shorter than in conventional systems. The electronics may include one or more of a control system circuit, a write driver, and/or a data buffer. The control system circuit generates a modified clock signal that has a fixed relation to phase and frequency of a bit-detected reference signal that corresponds to positions of patterned bits on the disc. The write driver writes outgoing data bits received from an external connection to off-head electronics directly to the writer synchronized with the modified clock signal. The data buffer stores and converts digital data bits sent from the off-head electronics to an analog signal that is synchronized with the modified clock signal.

Storage device and control method

According to one embodiment, a storage device includes a detector, a demodulator, a controller, and a recorder. When a user data item is split data including first data being at least part of a first code word and second data being at least part of a second code word, the controller sets a start position of the second data for forced search of the second code word on the basis of the position of a sync mark recorded in the recorder when the forced search of the first code word has succeeded.

AUDIO DIGITIZATION

A method of digitizing an audio track carried on an elongate recording medium, such as a movie film, includes transporting the recording medium containing the audio track past a reader to enable sequential reading of the audio track. The reading of the audio track generates an analog output signal. The method also includes sensing a rate of transportation of the recording medium, and sampling the analog output signal at a sampling rate determined on the basis of the sensed rate of transportation to digitize the analog output signal. A system for digitizing audio is also disclosed.

Multi-stage MISO circuit for fast adaptation

Systems and methods are disclosed for applying multi-stage multiple input single output (MISO) circuits for fast adaptation. An apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, a MISO circuit. The MISO circuit may include a first stage filter having a first number of taps and configured to filter signal samples received from the first reader and the second reader and produce first filtered samples. The MISO circuit may also include a second stage filter having a second number of taps greater than the first number, and be configured to receive the first filtered samples corresponding to the first reader and the second reader from the first filter stage, filter the first filtered samples to produce second filtered samples, and combine the second filtered samples to produce a combined sample output.

Determining bit aspect ratios for interlaced magnetic recording tracks

A method involves determining bit aspect ratios for interlaced tracks written to a magnetic recording medium. The interlaced tracks include top tracks that are written partially overlapping and interlaced with bottom tracks. Isolated test tracks are written at first different bit aspect ratios to determine a top bit aspect ratio that achieves a first target areal density for the isolated test tracks. Interlaced test tracks are written at second different bit aspect ratios to determine a bottom bit aspect ratio that achieves a second target areal density for the interlaced test tracks. Top test tracks of the interlaced test tracks are written at the top bit aspect ratio. The top and bottom bit aspect ratios are selected to subsequently write interlaced tracks on the magnetic recording medium.

On head microelectronics for write synchronization

The presently disclosed technology teaches integrating disc drive electronics into a transducer head. Decreased electrical transit times and data processing times can be achieved by placing the electronics on or within the transducer head because electrical connections may be made physically shorter than in conventional systems. The electronics may include one or more of a control system circuit, a write driver, and/or a data buffer. The control system circuit generates a modified clock signal that has a fixed relation to phase and frequency of a bit-detected reference signal that corresponds to positions of patterned bits on the disc. The write driver writes outgoing data bits received from an external connection to off-head electronics directly to the writer synchronized with the modified clock signal. The data buffer stores and converts digital data bits sent from the off-head electronics to an analog signal that is synchronized with the modified clock signal.