In some embodiments, an apparatus comprises: a static random access memory (SRAM) device. The SRAM device may have a bit cell array comprising a plurality of bit cells, the plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column of the plurality of columns operatively coupled to a pair of bit lines. The apparatus may comprise a controller configured to: assert a word line associated with a row; perform a sequence of write operations while the word line remains asserted, each write operation corresponding to a bit cell associated with a different column of the plurality of columns and the row, wherein the word line has an elevated voltage relative to a non-elevated voltage during at least a portion of the sequence of write operations; and de-assert the word line after the sequence of write operations are performed.

A deterministic apparatus comprising a deterministic near-compute memory communicatively coupled with and proximate to a deterministic processor. The deterministic near-compute memory comprises a plurality of data banks having a global memory address space, a control bus, a data input bus and a data output bus for each data bank. The deterministic processor is configured to initiate, via the control bus, retrieval of a set of data from the plurality of data banks. The retrieved set of data comprises at least one row of a selected one of the data banks passed via the data output bus onto a plurality of stream registers of the deterministic processor.

Methods, systems, and devices for dynamically configuring transmission lines of a bus between two electronic devices (e.g., a controller and memory device) are described. A first device may determine a quantity of bits (e.g., data bits, control bits) to be communicated with a second device over a data bus. The first device may partition the data bus into a first set of transmission lines (e.g., based on the quantity of data bits) and a second set of transmission lines (e.g., based on the quantity of control bits). The first device may communicate the quantity of data bits over the first set of transmission lines and communicate the quantity of control bits over the second set of transmission lines. In some cases, the first device may repartition the data bus based on different quantities of data bits and control bits to be communicated with the second device at a different time.

A memory is provided that is configured to practice two different modes of read operation, such as both a normal read operation and a burst-mode read operation. In one example, the memory is a pseudo-dual-port memory. The memory may include an address comparator to perform a time-division multiplexing to first compare a read address to a stored address and then to compare a write address to the stored address.

A memory device comprises a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit comprises a plurality of memory cells arranged along a second direction different from the first direction; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; and at least one column word line elongated along the second direction; wherein the memory cell comprises a storage cell configured to store data and at least two access transistors; wherein a control terminal of one of the at least two access transistors of the memory cell is coupled to the at least one column word line, and a control terminal of another one of the at least two access transistors of the memory cell is coupled to the corresponding word line.

Methods and apparatus monitor memory access activities of non-real-time processing engines to determine time intervals when the memory access activities are low. When such time intervals are found, the methods and apparatus perform burst memory access control for real-time processing engines by bursting data from a memory to a burst memory buffer, or from the burst memory buffer to the memory, to allow fast data access by the real-time processing engines.

A memory module including a row hammer counter chip, a memory system including the same, and a method of operating the memory system are provided. The memory module includes a plurality of data chips each of which is configured to store a data set corresponding to a plurality of burst lengths, and at least one row hammer counter chip including counter memory cells each of which is connected to a word line, among a plurality of word lines, for each of the plurality of data chips, wherein the at least one row hammer counter chip is configured to store in each of the counter memory cells connected to the word line, a number of times the word line is accessed for each of the plurality of data chips during a row hammer monitoring time frame.

A memory device with reduced latency is provided. The memory device includes a burst read mode with a burst length of M.sub.0 (M.sub.0 is an integer greater than or equal to 2), a global sense amplifier array, M.sub.0 local memory cell arrays <1> to <M.sub.0>, and M.sub.0 local sense amplifier arrays <1> to <M.sub.0>. A memory cell includes a transistor and a capacitor. A local memory cell array <J> (J is an integer from 1 to M.sub.0) is stacked over a local sense amplifier array <J>. The local memory cell array <J> comprises M.sub.0 blocks <J_1> to <J_M.sub.0> differentiated by row, The local sense amplifier array <J> in an idle state retains the data of the block <J_J>. The block <J_J> is specified when the local memory cell array <J> is the first local memory cell array to be accessed in a burst read mode.

A communication device includes a first client group in a first region; a second client group in a second region different from the first region; a first data hub configured to generate first burst data and a first control packet based on first client data received from the first client group; a second data hub configured to generate second burst data and a second control packet based on second client data received from the second client group; and a data transfer unit connected to the first data hub and the second data hub via a control protocol, the data transfer unit configured to, store the first burst data in a target memory based on the first control packet, and store the second burst data in the target memory based on the second control packet.

A memory circuit includes a memory array, a word line, and a bit line. The memory array includes a plurality of memories arranged in a matrix shape in a first direction and a second direction perpendicular to the first direction. The word line extends in the first direction and reads signals from the plurality of memories arranged in the first direction. The bit line includes a digit line connected to the plurality of memories arranged in the second direction and an output line connected to the digit line and extending in the first direction and transmits a signal from a memory corresponding to the word line to the output line as the word line reads a signal.